Arbiter PUF Circuit Using MOSFET Threshold Loss for Randomness
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Solution Overview
Problem
Traditional arbiter PUF circuits have large hardware expenditures due to the use of multiple transmission gates composed of two MOS transistors, leading to small delay differences between signal paths and poor randomness of responses.
Innovation Solution
A PUF circuit utilizing N stages of delay units with a structure that allows square signals to pass through in parallel or crossed manners, each stage comprising six inverters and four MOS transistors, reducing hardware expenditure by eliminating transmission gates and enhancing delay differences through threshold loss of MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transmission gates composed of two MOS transistors are used in traditional APUF circuits, then the circuit structure is complete and can control signal transmission, but the hardware expenditure increases and the delay difference between signal paths becomes small
Solution Approach 1:
The patent extracts and removes the transmission gate structure from the delay unit, keeping only the essential inverter components. This eliminates the complex complementary CMOS structure of transmission gates while retaining the core signal transmission and control functions through a simplified inverter-based architecture, directly reducing hardware expenditure.
Solution Approach 2:
The patent changes the transistor configuration from complementary CMOS (both PMOS and NMOS) to single-type MOS transistors in the delay unit. This parameter change in the circuit structure reduces the number of transistors per transmission path and increases threshold loss effects, thereby reducing hardware complexity while maintaining control functionality.
2Ease of operation
If transmission gates are used in traditional APUF circuits, then the circuit can operate with controlled signal paths, but the delay difference between first and second path square signals becomes small resulting in poor randomness
Solution Approach 1:
The patent changes the transistor type parameter from complementary CMOS to single-type MOS transistors, which introduces significant threshold loss in the transmission paths. This parameter change creates substantial delay differences between parallel signal paths due to the cumulative effect of threshold voltage drops across multiple MOS transistors, thereby improving the randomness of the PUF response.
Solution Approach 2:
The patent creates asymmetric delay characteristics between the first and second signal paths by using MOS transistors with inherent threshold loss. The asymmetric voltage drops and delay times in each path enhance the distinguishability of signal arrival times at the arbiter, improving the overall randomness and quality of the PUF output.
3Adaptability or versatility
If multiple transmission gates are used in traditional APUF circuits, then the circuit can provide abundant challenge-response pairs, but the hardware cost increases
Solution Approach 1:
The patent makes the delay unit universally applicable by using a standardized inverter-based structure with MOS transistors that can handle both signal transmission and threshold loss generation functions. This multi-functional design eliminates the need for separate transmission gate components, allowing the same structural unit to provide both control and randomness generation, thereby reducing hardware cost while maintaining versatility.
Solution Approach 2:
The patent merges the functions of transmission gate control and delay generation into a single integrated inverter-based structure. By combining signal routing and threshold loss effects in one unified component, the circuit achieves the same challenge-response pair functionality with reduced hardware complexity and lower implementation cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit reduces hardware costs and improves response randomness by minimizing the number of MOS transistors and increasing delay differences between signal paths, ensuring high-quality responses.
Implementation Method 1
the delay unit comprises six inverters and four MOS transistors... the four MOS transistors are all PMOS transistors or NMOS transistors... enhancing delay differences through threshold loss of MOS transistors
Data Source
AI summary
A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.