Arbiter for Shared Memory Processor Data Flow Arbitration
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Solution Overview
Problem
In storage devices like tape drives, shared memory configurations face challenges in efficiently managing access requests from both processors and data flow blocks, leading to performance degradation due to long process wait times and potential halts in host and servo processes, as conventional methods struggle to allocate sufficient bandwidth and prioritize access requests effectively.
Innovation Solution
A programmable arbiter is implemented to arbitrate access requests to shared memory, dividing data transfers into predetermined lengths, setting priorities for each transfer block, and limiting processor access to minimize interference with data flow transfers, ensuring required bandwidths are met while reducing processor access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a shared memory configuration is used between processor and data flow blocks, then the number of DRAM memories is reduced contributing to power consumption and cost reduction, but processor access latency increases due to competition for memory bandwidth
Solution Approach 1:
The arbiter dynamically switches between round-robin arbitration and processor-priority arbitration modes based on system state. When processor access is critical, the arbiter grants processor access requests preferentially, interrupting data flow transfers temporarily. This dynamic adaptation resolves the contradiction by allowing the shared memory to serve both purposes while minimizing processor wait time.
Solution Approach 2:
The system changes the arbitration parameter (arbitration mode) based on processor needs. The arbiter can switch between equal-bandwidth allocation for data flows and processor-preferred allocation, effectively changing how memory bandwidth is distributed. This parameter change allows the same shared memory to satisfy both power reduction requirements and processor performance requirements.
2Productivity
If processor access requests are given high priority in shared memory, then processor performance is improved, but data flow transfer rates may be degraded due to insufficient bandwidth allocation
Solution Approach 1:
The arbiter implements periodic round-robin arbitration for data flow blocks, ensuring that each block receives scheduled access to the shared memory. Between these periodic data flow allocations, the arbiter can insert processor access requests. This periodic structure guarantees minimum bandwidth for data flows while allowing processor access during allocated time slots, resolving the contradiction between processor performance and data flow transfer rates.
Solution Approach 2:
The arbitration scheme dynamically adjusts between processor-priority mode and round-robin data flow mode. When processor access is requested, the arbiter temporarily prioritizes the processor over data flows. When no processor access is needed, the arbiter switches to round-robin mode to ensure data flow blocks receive their required bandwidth. This dynamic switching resolves the contradiction by allowing both high processor performance and adequate data flow transfer rates at different times.
3Reliability
If round-robin arbitration is used for data flow blocks, then bandwidth allocation is fair among blocks, but processor access requests experience long wait times
Solution Approach 1:
The arbiter dynamically switches between round-robin arbitration and processor-priority arbitration modes based on system state. When processor access is critical, the arbiter grants processor access requests preferentially, interrupting data flow transfers temporarily. This dynamic adaptation resolves the contradiction by allowing the shared memory to serve both purposes while minimizing processor wait time.
Solution Approach 2:
The invention extracts processor access requests from the standard round-robin data flow arbitration sequence. When a processor access request arrives, the arbiter removes it from the normal data flow rotation and handles it with higher priority, temporarily suspending the round-robin sequence for data flows. This extraction allows processor requests to be serviced without being constrained by the fair but slow round-robin mechanism.
Data Source
AI summary
Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.