Arbitrary Width Integer Arithmetic Using Fixed-Width FFMA Elements

Solution Overview

Problem

Existing computer systems and GPUs face inefficiencies in performing integer arithmetic operations due to the need for dedicated 32-bit multipliers, which increase microcircuit real estate and power overhead, and augmenting FFMA units to 32 bits for both floating point and integer operations also results in increased power and space usage.

Innovation Solution

The method involves segmenting input operands into multiple sectors and performing multiply-add operations using existing fused floating point multiply-add (FFMA) elements, allowing for arbitrary width integer arithmetic through software-directed cycles, thus avoiding the need for additional hardware and optimizing power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a dedicated 32 bit multiplier is added to perform integer arithmetic, then integer arithmetic capability is improved, but microcircuit real estate and power consumption increase

Engineering Contradiction:

Improveinteger arithmetic capabilityVSAvoidmicrocircuit real estate

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent makes the existing 24-bit FFMA multiplier perform dual functions: it handles both floating-point operations (24-bit mantissa multiplication) and integer operations (32-bit integer multiplication) by selectively gating bits. This eliminates the need for a separate dedicated 32-bit multiplier while maintaining both capabilities, directly resolving the contradiction between versatility and area usage.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the existing multiplier by dynamically gating different bit portions based on the operation type. For integer operations, all 32 bits are enabled; for floating-point operations, only the lower 24 bits are active. This parameter switching allows one hardware element to serve multiple purposes without requiring additional circuitry.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If the FFMA multiplier is augmented to 32 bits for both floating point and integer operations, then versatility is improved, but real estate usage and overhead power increase

Engineering Contradiction:

Improvedual operation supportVSAvoidoverhead power

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent makes the existing 24-bit FFMA multiplier perform dual functions: it handles both floating-point operations (24-bit mantissa multiplication) and integer operations (32-bit integer multiplication) by selectively gating bits. This eliminates the need for a separate dedicated 32-bit multiplier while maintaining both capabilities, directly resolving the contradiction between versatility and area usage.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs dynamic bit gating control where the multiplier's active bit width changes based on the operation type. A control mechanism enables or disables specific bit portions of the multiplier and associated wiring, allowing the system to adapt its resource usage to the current computational needs, thereby reducing overhead power when full 32-bit capability is not required.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If the FFMA multiplier is augmented to 32 bits, then integer operation capability is improved, but connecting wire length and capacitive losses increase

Engineering Contradiction:

Improveinteger operation supportVSAvoidcapacitive losses

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent employs dynamic bit gating control where the multiplier's active bit width changes based on the operation type. A control mechanism enables or disables specific bit portions of the multiplier and associated wiring, allowing the system to adapt its resource usage to the current computational needs, thereby reducing overhead power when full 32-bit capability is not required.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent extracts and removes the unnecessary upper 8 bits from the multiplier circuit when performing floating-point operations. By physically disconnecting or gating off these unused bits and their associated connecting wires, the system eliminates the capacitive losses that would otherwise occur in the unused circuitry, while preserving the ability to enable full 32-bit operation when needed.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9600235B2Technique for performing arbitrary width integer arithmetic operations using fixed width elements

Publication Date: 2017.03.21 NVIDIA CORP

AI summary

One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.