Arbitrating Circuitry Parallel Multiplexing Latency Reduction
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Solution Overview
Problem
Existing arbitrating and multiplexing circuitry in data processing systems experiences performance limitations due to the serial nature of arbitration and multiplexing operations, which can restrict clock frequency and increase latency.
Innovation Solution
Implementing a parallel configuration where the first set of multiplexing levels operates in parallel with the arbitrating levels to perform a partial selection, followed by a series operation of the second set of multiplexing levels to complete the selection after arbitration is completed, reducing the overall processing time and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If arbitration and multiplexing operations are performed in series, then the circuit structure is simple, but the processing delay and latency increase
Solution Approach 1:
The patent applies preliminary action by performing partial multiplexing operations before the arbitration is complete. The first set of multiplexing levels operates in parallel with the arbitration tree, performing preliminary selection of inputs based on partial arbitration results. This allows the multiplexing process to start earlier and overlap with the arbitration process, reducing the total processing time without significantly increasing circuit complexity.
2Device complexity
If arbitration and multiplexing operations are performed in series, then the gate depth is reduced, but the clock frequency is restricted
Solution Approach 1:
The patent transitions from a one-dimensional serial execution model to a two-dimensional parallel execution model. The arbitration tree and multiplexing levels are arranged in a hierarchical structure where multiple multiplexing levels operate in parallel with different stages of the arbitration tree. This dimensional reorganization allows operations to proceed simultaneously rather than sequentially, increasing clock frequency without proportionally increasing gate depth.
3Loss of time
If more multiplexing levels are added to reduce latency, then the processing speed improves, but the gate depth of the multiplexing tree increases significantly
Solution Approach 1:
The patent segments the multiplexing function into multiple levels that can be distributed and executed in parallel with the arbitration tree. Instead of adding all multiplexing levels after arbitration completion, the multiplexing is divided into segments that correspond to different stages of the arbitration process. Each segment can be executed independently and in parallel, reducing latency without requiring a single deep multiplexing path.
Data Source
AI summary
Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.