Arbitration Circuit Priority Cancellation Mechanism

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Solution Overview

Problem

In multi-bus arbitration systems, high-priority transactions are often delayed as they wait for the completion of low-priority transactions, leading to inefficient use of bus resources and reduced performance due to the lack of a mechanism to cancel and prioritize transactions effectively.

Innovation Solution

An arbitration circuit with a first-in-first-out buffer and a control circuit that monitors transactions and cancels low-priority transactions to allow high-priority transactions to be executed immediately, utilizing a second buffer to manage and prioritize transactions based on priority levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transfers for all requests are executed in parallel when no conflict is detected, then bus utilization is improved, but high-priority requests may be delayed waiting for low-priority requests to complete

Engineering Contradiction:
Improvebus utilizationVSAvoidhigh-priority request delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a monitoring mechanism that detects high-priority requests in advance before they are fully processed. When a high-priority request is detected, the system proactively cancels ongoing low-priority transactions and redirects the bus to the high-priority request, preventing delay rather than reacting after the fact.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The arbitration circuit incorporates a monitoring mechanism that continuously observes the buffer contents and request priorities. This feedback loop enables the system to detect when a high-priority request is present and automatically adjust the transaction execution sequence, canceling low-priority requests if necessary to prioritize high-priority ones.

Inventive Principle:
Principle #23Feedback

2Speed

If low-priority requests are canceled to prioritize high-priority requests, then high-priority request execution is improved, but system complexity increases due to cancel mechanisms

Engineering Contradiction:
Improvehigh-priority request execution speedVSAvoidarbitration circuit complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces a dedicated monitoring mechanism as an intermediary component that sits between the buffer and the arbitration logic. This monitoring mechanism simplifies the overall system by centralizing the priority detection and cancel request generation functions, making the complexity localized rather than distributed throughout the arbitration circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The arbitration circuit is segmented into distinct functional components: a monitoring mechanism that detects priority conditions, a buffer that stores transaction information, and an arbitration logic that executes cancel requests. This segmentation allows each component to be optimized independently and simplifies the overall design by dividing the complex arbitration function into manageable modules.

Inventive Principle:
Principle #1Segmentation

3Loss of time

If high-priority transactions are executed immediately by canceling low-priority ones, then processing delay is reduced, but loss of information occurs when cancel requests fail

Engineering Contradiction:
Improvetransaction processing delayVSAvoidtransaction data loss
Core Design Contradiction:
Loss of timeVSLoss of information

Solution Approach 1:

The patent introduces a buffer that stores transaction information before execution. This buffer acts as a cushion that protects against information loss: if a cancel request fails, the original transaction data remains preserved in the buffer and can be re-transmitted, ensuring no permanent data loss occurs during the priority arbitration process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9703730B2Arbitration circuit and processing method of arbitration circuit
Publication Date: 2017.07.11 SOCIONEXT INC
  • US9703730B2 patent drawing
  • US9703730B2 patent drawing
  • US9703730B2 patent drawing

AI summary

In an arbitration circuit, transactions output from a plurality of master circuits are stored in a first-in-first-out type first buffer, and when a high-priority transaction higher in priority than one of the stored transactions is output from one of the plural master circuits, a cancel request of a low-priority transaction lower in priority than the high-priority transaction, out of the stored transactions, is output to a second buffer in a slave circuit, and when the cancel request is successful, the high-priority transaction is output to the slave circuit, and after the high-priority transaction is output to the slave circuit, the low-priority transaction whose cancel request is successful is output to the slave circuit.