Arbitration Circuitry for Dual-Port Memory Area Reduction
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Solution Overview
Problem
Conventional dual-port memory cells require more area than single-port cells and existing techniques for achieving synchronous dual-port functionality, such as double-clocking, limit memory performance and cannot support asynchronous operations.
Innovation Solution
The implementation of memory circuitry with single-port memory elements and an arbitration circuit that manages memory access requests from multiple ports using either a single clock for synchronous operations or separate clocks for asynchronous operations, allowing for efficient dual-port functionality without increasing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional eight-transistor dual-port memory cells are used, then dual-port functionality is achieved, but area occupation increases to more than double that of single-port cells
Solution Approach 1:
The patent merges two single-port memory cells into a dual-port memory cell by sharing common bit lines and control circuitry between them. The first and second single-port memory cells share bit line pairs, allowing both ports to access the same memory array through shared resources, thereby reducing the total area compared to having completely separate dual-port cells.
Solution Approach 2:
The patent implements multi-functionality by enabling the memory cell to operate in multiple modes: it can function as a single-port memory cell or as a dual-port memory cell. The control circuitry can configure the shared bit lines and access transistors to serve either one port or two ports dynamically, providing universal functionality that adapts to different operational requirements.
2Area of stationary object
If double-clocking techniques are used to achieve synchronous dual-port functionality, then area is reduced, but memory performance is limited and asynchronous operations cannot be supported
Solution Approach 1:
The patent introduces dynamic configurability through control signals that can switch the memory cell operation between synchronous and asynchronous modes. The control circuitry responds to enable signals and clock phases dynamically, allowing the same hardware structure to adapt its timing behavior based on operational requirements, thus supporting both synchronous dual-port and asynchronous operations.
Solution Approach 2:
The patent changes operational parameters by allowing the memory cell to operate with different clocking schemes. When operating asynchronously, the cell can be accessed during both high and low clock phases independently for each port, rather than being constrained to alternating phases. This parameter flexibility enables support for different clock frequencies and phases while maintaining area efficiency.
Data Source
AI summary
An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.