Arbitration Circuitry Tie-Break Mechanism

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Solution Overview

Problem

In data processing systems, the comparison of priority values for arbitration can constrain the maximum speed of transactions and introduce bottlenecks, especially when tie-break mechanisms are added to handle inputs with equal priority values, leading to potential starvation and reduced throughput.

Innovation Solution

The implementation of arbitration circuitry that generates tie-break values and appends these as least significant bits to priority values, allowing for a single comparison to perform both arbitration and tie-break selection, using a binary tree comparator to efficiently distinguish between inputs with the same or different priority values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If tie-break mechanisms are added to handle inputs with equal priority values, then fairness in selection is improved, but the critical path length increases and maximum throughput decreases

Engineering Contradiction:
Improvefairness in arbitrationVSAvoidmaximum throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the priority comparison and tie-break selection into a single comparator operation. By appending tie-break bits to the priority values, the system performs both functions in one comparison cycle, eliminating the need for separate tie-break logic and reducing the critical path delay.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The tie-break bits are prepared and appended to priority values in advance, before the comparison operation. This preliminary preparation ensures that when the comparison occurs, both priority evaluation and tie-break resolution are already configured, enabling single-cycle arbitration without additional delay.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple comparison stages are used to handle tie-break situations, then selection fairness is improved, but the arbitration time increases

Engineering Contradiction:
Improvecontrolled tie-break selectionVSAvoidarbitration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple comparison functions into a single comparator by integrating tie-break bits with priority values. This merging allows the comparator to resolve both priority conflicts and tie-break scenarios in one operation, reducing arbitration time from multiple cycles to a single cycle.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent adds tie-break bits as an additional dimension to the priority value structure. By appending these bits to the least significant positions, the system creates an extended priority space that naturally resolves ties without requiring additional comparison stages, effectively solving the problem in the same time dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9507737B2Arbitration circuitry and method
Publication Date: 2016.11.29 ARM LTD
  • US9507737B2 patent drawing
  • US9507737B2 patent drawing
  • US9507737B2 patent drawing

AI summary

Arbitration circuitry is provided to select an output from between multiple inputs each having an associated priority value. A tie-break value is appended to the least significant bits of each of the priority values to form extended priority values before those extended priority values are compared. Thus, if two priority values are equal, then the appended tie-break bits are used to determine which of the two inputs will be selected as having the higher priority.