Arbitration Logic for Embedded Shared Buffer Egress
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Solution Overview
Problem
In embedded systems, the contention for access to a centralized memory core leads to performance issues due to latency and the need for direct data access without processor intervention, especially in computationally intensive tasks like audio and video processing, where data may be trapped between the shared buffer and co-processors if not properly managed.
Innovation Solution
A logic module with arbitration logic and a counter is introduced to support speculative read accesses, allowing co-processors to directly access shared buffers without processor assistance, using pipeline stages and a counter to track and adjust addresses for data that has not been delivered, ensuring efficient data handling and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If co-processors directly access shared buffers without processor intervention, then data processing speed is improved, but data may be trapped between shared buffer and co-processors if not properly managed
Solution Approach 1:
The patent implements a feedback mechanism where the arbitration logic module continuously monitors the status of data transfer between the shared buffer and co-processors. The module uses feedback signals to detect when data has been successfully delivered or is trapped, and adjusts arbitration decisions accordingly to prevent data loss and ensure reliable delivery while maintaining high processing speed.
Solution Approach 2:
The arbitration logic module serves as an intermediary between the shared buffer and multiple co-processors. It manages direct access requests from co-processors to the shared buffer, mediating the transfer process to enable fast direct access while simultaneously ensuring proper data delivery through its arbitration and control functions.
2Device complexity
If a centralized memory core is shared among multiple processing sources, then device complexity is reduced, but contention for access leads to performance degradation
Solution Approach 1:
The arbitration logic module performs preliminary actions by pre-establishing access grants and managing data transfer queues before actual data access occurs. It proactively handles arbitration between competing processors, preparing the system for efficient data access while maintaining the simplicity of the shared memory architecture.
Solution Approach 2:
The patent implements dynamic arbitration where the arbitration logic module adaptively adjusts access rights and data transfer timing based on real-time system conditions. This dynamic management allows multiple processors to efficiently share the centralized memory core without rigid access protocols, maintaining both architectural simplicity and high productivity.
3Productivity
If pipeline stages are used to store data read from shared buffer, then data handling efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the data path into multiple pipeline stages, with each stage handling a specific aspect of data transfer from the shared buffer to co-processors. This segmentation enables parallel processing of multiple data items simultaneously, improving data handling efficiency while keeping each individual pipeline stage relatively simple and manageable.
Data Source
AI summary
In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a memory core having a shared buffer, and an arbitration logic module for receiving a destination ready signal from a processing source of a plurality of processing sources. The device also comprises at least one pipeline stage for storing at least one piece of data read from the shared buffer, and at least one matching pipeline stage storing at least one valid signal associated with the at least one piece of data read from the shared buffer. The device also comprises a counter for storing a value, wherein the value represents a number of pieces of data read from the shared buffer, but have not been delivered to the processing source.