Arbitration Module for CPU Peripheral Memory Access Priority
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current systems for arbitrating memory access between a central processing unit (CPU) and peripheral devices, such as video controllers, often result in data loss when both have the highest priority level, leading to potential losses in image frames in real-time systems like camera-based driver assistance and video processing, due to the lack of configurable priority logic in standard bus protocols.
Innovation Solution
An arbitration module is introduced to dynamically adjust the CPU priority level based on the peripheral device's priority level, specifically reducing the CPU priority from the highest level when both are at maximum to prevent data loss, and adjusting it according to the buffer fullness or emptiness for write or read operations respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU is given the highest priority for memory access, then CPU can execute without stopping, but peripheral device may lose data when buffer overflows
Solution Approach 1:
The arbitration module dynamically adjusts CPU priority level based on real-time buffer status. When peripheral device buffer is full and both CPU and peripheral device request highest priority, the arbitration module reduces CPU priority to allow peripheral device access, preventing buffer overflow and data loss while maintaining CPU high productivity during normal operation
Solution Approach 2:
The system implements feedback mechanism where the arbitration module continuously monitors buffer status from peripheral devices and adjusts CPU priority levels accordingly. This feedback loop ensures that CPU priority is reduced only when necessary (when buffer is full) and restored when buffer has capacity, balancing productivity and reliability
2Reliability
If peripheral device is given highest priority to prevent data loss, then data loss is prevented, but CPU execution is interrupted
Solution Approach 1:
Instead of statically assigning highest priority to peripheral device, the system dynamically adjusts CPU priority level based on buffer status. This dynamic approach ensures peripheral device gets timely access when buffer is full (preventing data loss) while CPU maintains highest priority during normal operation (maintaining productivity)
3Device complexity
If standard bus protocol is used without configurable priority logic, then system is simple and compatible, but cannot prevent data loss in real-time systems
Solution Approach 1:
The arbitration module serves as an intermediary component between CPU and peripheral devices, adding intelligent priority arbitration capability without replacing standard bus protocols. This mediator component enables configurable priority logic and real-time data loss prevention while maintaining compatibility with existing systems
Solution Approach 2:
The arbitration module provides universal priority arbitration service for multiple CPU and peripheral device combinations. It handles various priority scenarios (CPU only, peripheral only, both requesting) and buffer conditions (full, partially full, empty) through a single multi-functional component
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Arbitrating memory access between a central processing unit CPU (106) and a peripheral device to main memory (102). The memory access to and from the main memory (102) by the CPU (106) and memory access to and from the main memory (102) by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level An arbitration module (200) is provided externally to the CPU (106), to the peripheral device and to the memory controller (104). The arbitration module (200) receives the peripheral device priority level. When the CPU (106) priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module (200) outputs to the memory controller (104) a new CPU priority level less than the highest available priority level.