Arbitration Sub-Queues for Memory Circuit Bus Efficiency
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Solution Overview
Problem
In computing systems, particularly system-on-a-chip (SoC) designs, the communication bus can become a bottleneck due to backlogs from a series of write requests, leading to inefficiencies in memory request processing and reduced performance.
Innovation Solution
Implementing a queue manager circuit with multiple bus queues and an arbitration circuit to distribute and prioritize memory requests based on availability of the data bus, ensuring a mix of read and write requests are processed efficiently, thereby reducing idle cycles in the communication bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple write requests are processed sequentially, then data can be transferred to memory, but the data bus remains unavailable for subsequent read requests, creating idle cycles
Solution Approach 1:
The patent segments the memory request queue into separate read request queue and write request queue. This segmentation allows the arbitration circuit to independently manage read and write requests, enabling read requests to be processed when the data bus is unavailable for write operations, thereby eliminating idle cycles and improving overall processing efficiency
Solution Approach 2:
The patent implements dynamic arbitration that adapts its behavior based on real-time availability of the data bus. The arbitration circuit dynamically selects which queue (read or write) to process based on current bus conditions, allowing flexible switching between request types to maximize utilization and reduce idle time
2Productivity
If a single bus queue is used to store memory requests, then the structure is simple, but the communication bus cannot efficiently handle mixed read and write requests, reducing performance
Solution Approach 1:
The patent divides the single bus queue into separate read request queue and write request queue within the queue manager circuit. This segmentation enables specialized handling of read and write requests, improving communication bus efficiency by ensuring appropriate request types are processed when bus resources are available, while the added structural complexity is localized to the queue manager rather than the entire system
3Quantity of substance
If write requests with large data operands are processed, then data transfer completes, but the data bus is occupied for multiple bus cycles, preventing concurrent read operations
Solution Approach 1:
The patent segments request processing into separate read and write queues, allowing read requests to be queued and processed independently of write requests. When a write request with large data operand occupies the data bus for multiple cycles, read requests can still be processed during these cycles using the command bus, thereby maintaining concurrent request processing capability while preserving data transfer capacity
Solution Approach 2:
The patent introduces a dimensional separation between read and write request processing by using separate queues. This allows the system to handle read and write operations in different processing dimensions simultaneously, enabling read requests to proceed independently of write-related data bus occupancy and thereby increasing concurrent processing capability
Data Source
AI summary
An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.