Arbitration Unit Using Non-Stalling Indications to Prevent Deadlocks
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Solution Overview
Problem
Integrated circuits face deadlocks when multiple master circuits submit requests to multiple target circuits, leading to a situation where no requests are serviced due to competition and queuing constraints.
Innovation Solution
Incorporating an arbitration unit that uses indications submitted with each request to determine the order of servicing, ensuring that requests are processed based on their initial submission order, and utilizing separate latch stages for indications that do not stall even if the associated requests are held up, preventing deadlocks by prioritizing earlier submitted requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If requests are held in latch stages when targets are unavailable, then requests are queued for later servicing, but deadlock occurs when multiple masters compete for multiple targets
Solution Approach 1:
The patent applies preliminary action by having master circuits submit indications of their requests before the requests are actually serviced. These indications are propagated through indication latch stages independently of the request data, allowing the arbitration unit to determine the submission order in advance and make arbitration decisions that prevent deadlock before it occurs.
Solution Approach 2:
The patent introduces an intermediary mechanism - the indication signal separate from the request data - that mediates between master circuits and the arbitration unit. This indication acts as a placeholder or marker that allows the arbitration unit to track request submission order without being blocked by the actual request data stalling in the queue, thus preventing deadlock while maintaining proper servicing order.
2Ease of operation
If requests are processed in submission order, then fairness is maintained, but system responsiveness decreases due to queuing delays
Solution Approach 1:
The indication is submitted and propagated in advance of the actual request servicing, allowing the arbitration unit to establish the submission order beforehand. This preliminary indication submission enables the system to maintain fair ordering without requiring requests to physically queue in sequence, reducing actual waiting time while preserving fairness.
3Measurement precision
If indication latches operate independently of request latches, then arbitration accuracy improves, but circuit complexity increases
Solution Approach 1:
The patent segments the latch functionality into two independent parts: request latch stages that hold the actual request data, and indication latch stages that hold only the submission order information. This segmentation allows each latch type to be optimized for its specific function - request latches for data integrity and indication latches for timing accuracy - improving arbitration precision without requiring a complete redesign of the entire latch system.
Data Source
AI summary
Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.