Arc-Based Debugging for Static Timing Analysis
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Solution Overview
Problem
Current systems lack arc-based debugging capabilities for extracted timing models, making it cumbersome to debug specific timing arcs in electronic design analysis, and existing methods are limited to reporting mechanisms without detailed debugging functionality.
Innovation Solution
A computer-implemented method for performing static timing analysis that allows for arc-based debugging by receiving timing arcs specified by source and sink pins, generating worst timing paths, and providing characterization information without requiring a model extraction phase, using a debugging platform to map extracted timing models to netlist objects and display results on a graphical user interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If current reporting mechanisms are used to debug timing arcs, then timing information can be obtained, but the debugging process is cumbersome and counter intuitive requiring users to browse the design and determine combinations of interest
Solution Approach 1:
Instead of requiring users to browse the design and determine timing arc combinations (traditional approach), the patent inverts the process by allowing users to directly specify timing arcs of interest and automatically retrieving the relevant timing paths and characterization information. This reversal makes the debugging process intuitive and efficient.
Solution Approach 2:
The patent introduces an intermediary debugging platform that sits between the user and the complex timing analysis data. This platform receives user-specified timing arcs, automatically queries the extracted timing models and netlist objects, and presents the results in a user-friendly format, eliminating the need for users to manually browse and combine multiple data sources.
2Productivity
If extracted timing models are used for hierarchical implementation, then rapid top-level timing analysis is achieved, but detailed arc-based debugging capabilities are lacking
Solution Approach 1:
The patent segments the timing analysis system into distinct components: extracted timing models for rapid top-level analysis, netlist objects for detailed information, and a debugging platform that selectively queries these segments based on user needs. This segmentation allows both rapid analysis and detailed debugging to coexist efficiently.
Solution Approach 2:
The debugging platform is designed with multi-functionality, serving both rapid timing analysis and detailed arc-based debugging through a single unified interface. It can handle both high-level timing verification and low-level arc characterization without requiring separate tools or processes.
3Loss of information
If model extraction phase is performed to obtain timing information, then detailed timing characteristics are available, but the process is time-consuming and requires timing updates
Solution Approach 1:
The patent performs preliminary model extraction during the design phase to create extracted timing models and establish mappings to netlist objects. Once this preliminary work is done, the debugging platform can quickly query and retrieve timing information without requiring repeated model extraction or timing updates, thus preserving information completeness while minimizing time loss.
Data Source
AI summary
The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design at a debugging platform without performing a model extraction phase and mapping one or more extracted timing models (“ETM”) to one or more netlist objects associated with the electronic design. Embodiments may further include receiving, at the debugging platform, at least one timing arc specified by a source pin and a sink pin, wherein the at least one timing arc is associated with the electronic design. Embodiments may also include generating a worst timing path based upon, at least in part, the received at least one timing arc. Embodiments may further include generating characterization information for the at least one timing arc based upon, at least in part, one or more user-specified boundary conditions.