Anti-Reflective Coating Etching for Low Line Edge Roughness
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Solution Overview
Problem
Current integrated circuit manufacturing technologies face challenges in shrinking transistor sizes while maintaining performance, power reduction, and cost efficiency, particularly in balancing critical dimension (CD) shrinkage with minimal line edge roughness and avoiding increased copper line resistance.
Innovation Solution
The method involves forming a layer stack with an anti-reflective coating layer over a masking layer, followed by a photoresist layer, and using a low-pressure polymer burst with a non-oxidizing gas mixture to etch the anti-reflective coating layer, forming a polymer layer over resist lines, which helps in shrinking critical dimensions without increasing line edge roughness and maintaining through pitch CD bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional etching methods are used to shrink critical dimensions, then transistor size is reduced, but line edge roughness increases
Solution Approach 1:
The patent changes the etching parameters by using a polymer burst process with specific gas compositions (CHF3, CF4, C4F8) and controlling pressure conditions to achieve smooth line edges while shrinking critical dimensions. The polymer deposition during etching modifies the surface properties to reduce roughness.
Solution Approach 2:
The patent introduces a polymer layer as an intermediary substance during the etching process. This polymer acts as a mediator that protects the line edges from roughening while allowing the etching to proceed, thereby maintaining manufacturing precision during dimension shrinkage.
2Productivity
If critical dimensions are shrunk to increase transistor density, then more transistors fit in the same area, but through pitch CD bias increases
Solution Approach 1:
The patent modifies etching parameters including gas flow rates, pressure, and temperature to control the polymer burst process. These parameter changes enable consistent etching across different pitch sizes, maintaining through pitch CD bias control while achieving the required critical dimension shrinkage for higher transistor density.
Solution Approach 2:
The patent employs a periodic or pulsed etching process where the polymer burst is applied in controlled intervals. This periodic action allows for uniform material removal and consistent CD control across varying pitch dimensions, preventing CD bias accumulation.
3Productivity
If oxidizing gas mixtures are used for etching, then etching speed increases, but ultra-low k dielectric material is damaged
Solution Approach 1:
The patent uses an inert or non-oxidizing atmosphere by selecting gas mixtures that do not contain oxidizing components. The polymer burst process employs gases like CHF3, CF4, and C4F8 which create a protective environment during etching, preventing oxidation damage to the ultra-low k dielectric while maintaining adequate etching speed through polymer-mediated material removal.
Solution Approach 2:
The patent replaces direct chemical etching mechanisms with a polymer-mediated process. Instead of relying on chemical reactions that could damage the dielectric, the mechanical action of polymer deposition and subsequent removal provides controlled material extraction that protects the underlying ultra-low k dielectric structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces line edge roughness, minimizes CD bias variation, and enhances manufacturing efficiency by shrinking critical dimensions while maintaining consistent through pitch CD bias, thus improving the yield and performance of semiconductor devices.
Implementation Method 1
a low-pressure polymer burst with a non-oxidizing gas mixture to etch the anti-reflective coating layer, forming a polymer layer over resist lines
Data Source
AI summary
A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.