ARC Layer Blocks Self-Aligned Implants in BCD IC Gates
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Solution Overview
Problem
In advanced semiconductor ICs, the reduced thickness of polysilicon gate layers fails to effectively block self-aligned implants, leading to threshold voltage shifts and performance degradation in bipolar and CMOS devices due to reduced blocking power with technology scaling.
Innovation Solution
The method involves forming an anti-reflective coating (ARC) layer on the polysilicon gate, leaving a portion of it intact during self-aligned ion implantation to act as an additional implant blocking layer, enhancing the gate stack's blocking capability and maintaining reflectivity during polysilicon gate patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polysilicon gate layer thickness is reduced for technology scaling, then device size and power consumption are improved, but implant blocking capability deteriorates leading to threshold voltage shifts
Solution Approach 1:
The patent combines polysilicon gate material with anti-reflective coating (ARC) material to form a composite gate stack. The ARC layer serves dual purposes: maintaining optical reflectivity for patterning and providing additional implant blocking capability. This composite structure allows the polysilicon layer to be thinner while the combined stack maintains sufficient blocking power against self-aligned implants.
Solution Approach 2:
The anti-reflective coating layer performs multiple functions: (1) maintains reflectivity during polysilicon gate patterning for accurate photolithography, and (2) provides additional implant blocking capability when left intact during self-aligned implantation. This multi-functional use of the ARC layer resolves the contradiction between scaling and blocking capability.
2Manufacturing precision
If ARC layer is removed after polysilicon gate formation, then gate cleanliness is improved, but implant blocking capability is lost
Solution Approach 1:
The patent performs polysilicon gate patterning while the ARC layer is still present, utilizing its reflectivity for accurate pattern formation. The ARC layer is then strategically retained (not removed) to serve as an additional blocking layer during subsequent self-aligned implantation. This sequencing of actions allows both good gate definition and maintained blocking capability.
Solution Approach 2:
The ARC layer is selectively retained only in regions where implant blocking is needed (over the gate areas), while being removed in other regions. This local retention strategy maintains implant blocking capability where required without compromising overall process cleanliness or causing interference in other device regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively blocks high-energy self-aligned implants, such as LDD and DWELL, thereby maintaining device performance and preventing threshold voltage shifts, while allowing for technology scaling without compromising gate stack reflectivity.
Implementation Method 1
the ARC layer absorbs radiation waves, such as conventional deep ultraviolet (DUV) radiation. Being absorbed by the ARC layer, the radiation waves are prevented from undesirably reflecting off the underlying layer
Implementation Method 2
At least one self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates for blocking the ion implantation from reaching the semiconductor surface under the polysilicon gates
Data Source
AI summary
A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.