3D Arch-Channel TFT Layout for Higher On-State Current

The patent transitions from a conventional planar channel structure to a three-dimensional channel structure where the active layer forms arches that surround the gate electrode in multiple dimensions. This spatial transformation allows the channel to extend vertically and radially around the gate, effectively increasing the channel width without proportionally increasing the planar footprint of the device, thereby improving on-state current while controlling TFT area.

The active layer is designed to surround and enclose the gate electrode, forming a nested configuration where the channel structure contains the gate within its arches. This nesting arrangement maximizes the channel width by utilizing the space around the gate electrode, allowing current to flow through multiple pathways simultaneously, thus enhancing on-state current density within a compact area.

By forming arches that extend vertically and surround the gate electrode, the channel width is effectively increased in the vertical and radial dimensions rather than expanding horizontally. This allows the TFT to maintain a small planar area for high aperture ratio while achieving sufficient channel width for adequate on-state current through multi-dimensional channel formation.

The active layer is strategically positioned to form arches at specific locations around the gate electrode, concentrating the channel structure where it most effectively controls current flow. This localized optimization ensures maximum current conduction capability within the minimal necessary area, improving on-state current without compromising aperture ratio.