Arched Source/Drain Contact Structure for Gate Short Isolation
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Solution Overview
Problem
As semiconductor devices scale down, reliable interconnect structures become increasingly challenging to maintain, particularly due to the risk of accidental shorts between gate electrodes and source/drain contacts during the etching process, which complicates the manufacturing of three-dimensional transistors like FinFETs.
Innovation Solution
The process involves recessing source/drain contacts and capping them with a conductive layer and an overlying dielectric capping layer, which isolates the contacts from gate electrodes and reduces contact resistance, preventing accidental shorts by ensuring the conductive layers are not in direct contact with the gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain contacts are recessed and capped with conductive and dielectric layers, then reliability is improved by preventing shorts, but device complexity increases due to additional manufacturing steps
Solution Approach 1:
The source/drain contacts are recessed below the gate electrode level before finalization of the gate structure. This preliminary action prevents potential shorts between source/drain contacts and gate electrodes, ensuring reliability before subsequent manufacturing steps are completed.
Solution Approach 2:
A dielectric capping layer is introduced as an intermediary between the conductive source/drain contacts and the gate electrode. This dielectric layer acts as a mediator that electrically isolates the conductive elements, preventing shorts while allowing the structure to maintain its functional integrity.
2Reliability
If the contact area between source/drain contacts and via structures is increased, then contact resistance is reduced, but manufacturing precision requirements increase due to the arched top surface
Solution Approach 1:
The top surface of the source/drain contact structure is formed with a convex or arched curvature instead of a flat surface. This curved geometry increases the effective contact area with the via structure, reducing contact resistance. The curvature is achieved through controlled deposition processes that naturally form the domed shape.
Solution Approach 2:
The deposition parameters of the conductive capping layer are optimized to control the formation of the convex top surface. By adjusting deposition conditions such as temperature, pressure, and material flux, the contact area and curvature radius are controlled to achieve optimal contact resistance while maintaining manufacturability.
Data Source
AI summary
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate electrode layer formed over a substrate and a gate spacer structure formed over a sidewall of the gate electrode layer. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate spacer structure and separated from the gate electrode layer by the gate spacer structure. The source/drain contact structure includes a conductive base portion formed over a source/drain region in the substrate and a conductive capping portion with an arched top surface formed over the conductive base portion. The top surface of the conductive base portion is lower than the top surface of the gate electrode layer. The semiconductor device structure further includes a first dielectric capping layer formed over the source/drain contact structure.