Constant-Frequency Architectural Timer for DVFS Clock Synchronization
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Solution Overview
Problem
Microprocessors with dynamic voltage frequency scaling (DVFS) face synchronization issues due to varying core clock frequencies, making it challenging to provide a constant timer signal necessary for software synchronization and communication between cores and other components.
Innovation Solution
A method and circuit that generate a constant timer signal using a reference clock signal, which calculates differences in gray code values to increment a recursive timer signal, allowing the timer signal to be synchronized with the core clock domain, regardless of the core clock frequency, using a multiplexer and synchronization latches to maintain synchronization and power savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage frequency scaling is applied to reduce power consumption, then power consumption is reduced, but the core clock frequency becomes variable causing synchronization issues
Solution Approach 1:
The patent introduces an intermediary constant timer signal that is derived from the variable core clock frequency but maintains constant frequency characteristics. This intermediary signal acts as a mediator between the variable core clock and software components that require constant timing, allowing DVFS to operate while maintaining synchronization reliability.
Solution Approach 2:
The patent changes the parameter of the timer signal from variable (directly tied to core clock frequency) to constant (independent of core clock frequency variations). By decoupling the timer signal frequency from the core clock frequency through division and selection logic, the system maintains reliable synchronization while allowing the core clock frequency to vary for power management.
2Use of energy by stationary object
If the core clock frequency is reduced for power saving, then power consumption is reduced, but the timer signal cannot maintain constant frequency for software synchronization
Solution Approach 1:
The patent segments the clock domain into two independent parts: the variable core clock domain for power-efficient processing and the constant timer signal domain for software synchronization. By dividing the clocking function into separate segments with different frequency characteristics, the system achieves both power saving and ease of software operation.
Solution Approach 2:
The patent implements dynamic frequency selection where the timer signal can adapt to different core clock frequencies while maintaining its own constant frequency. The dynamic logic selectively divides or passes through clock cycles based on the current operating conditions, allowing the system to dynamically adjust power consumption without affecting software synchronization.
3Loss of energy
If DVFS techniques are used to adjust operating frequency, then power consumption is reduced, but synchronization between cores and external components becomes problematic
Solution Approach 1:
The constant timer signal serves as a stable intermediary that mediates between the variable core clock and external components requiring stable timing. This intermediary maintains frequency stability independent of core clock variations, enabling DVFS operation while preserving stable timing for external communications and inter-core synchronization.
Data Source
AI summary
Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.