Architecture-Guided Placement for Chip Floorplan Timing
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Solution Overview
Problem
Conventional Place and Route (P&R) tools in semiconductor chip design lack the use of overall chip architecture information, leading to inefficient initial placement of logic gates, which results in increased incremental changes and potential failure to meet timing constraints, especially in large chips with high target speeds.
Innovation Solution
The solution involves using the overall chip architecture to guide P&R by identifying preferred locations for architectural units within the floorplan, constraining their placement to satisfy system-level constraints such as wire length, timing path delay, and power, through the creation of a grid overlaying the chip floorplan and assigning architectural units to grid elements, thereby controlling cell placement and optimizing initial placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional P&R tools are used without architecture information, then the placement process is simpler, but the number of incremental changes needed increases and timing constraints may not be met
Solution Approach 1:
The patent applies preliminary action by performing architecture-guided initial placement before the conventional iterative P&R process. The system identifies architectural units, determines their connectivity, and assigns preferred locations based on architecture information in advance. This preliminary placement step provides a better starting point that reduces the number of incremental changes needed in subsequent iterations, improving timing constraint satisfaction without significantly increasing overall process complexity.
Solution Approach 2:
The patent introduces an intermediary component that bridges architecture information and P&R placement. This intermediary process analyzes architectural unit connectivity, computes preferred locations, and generates initial placement assignments that guide the conventional P&R tool. By inserting this intermediary layer, the system leverages architecture information to improve timing results while maintaining compatibility with existing P&R workflows.
2Productivity
If P&R tools focus primarily on minimizing wire length, then placement computation is faster, but timing performance deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the placement optimization approach for different cell types based on their functional characteristics. The system identifies architectural units and their connectivity patterns, then applies architecture-guided placement specifically to logic cells within these units while allowing standard wire-length optimization for other cells. This localized application of architecture-aware placement improves timing performance for critical paths without significantly increasing overall computation time.
Solution Approach 2:
The system performs preliminary architecture-based placement for logic cells before the main iterative optimization process. By pre-positioning logic cells according to architectural connectivity information, the system reduces the computational burden during iterative timing optimization, maintaining faster computation speeds while improving final timing performance.
3Loss of time
If architecture-guided initial placement is performed, then the number of incremental changes decreases and timing convergence improves, but the initial placement process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the placement process into distinct phases: architecture analysis, unit identification, connectivity determination, preferred location assignment, and initial placement generation. Each phase handles a specific aspect of the problem, making the overall complex process more manageable and systematic. The segmentation allows the system to leverage existing architecture information while adding placement guidance in a structured manner.
Solution Approach 2:
The patent introduces an intermediary process that translates architecture information into placement constraints and preferences. This intermediary layer processes architectural unit connectivity and generates preferred location assignments without requiring complete redesign of the placement system. By acting as a mediator between architecture description and placement algorithms, the system reduces initial placement complexity while achieving timing convergence benefits.
Data Source
AI summary
On-chip data transport network architectural units are assigned preferred placement locations based on architecture-level constraints. The preferred placement locations are used to generate placement constraints for a place and route tool. The placement constraints are applied to cells that are synthesized from each architectural unit. Constraints are blockages, fences, regions, and guides. Preferred placement locations are mapped to grid elements. Each grid elements defines a cell placement constraint.