Architecture-Specific Algorithm Generation Using Reconfigurable Blocks
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Solution Overview
Problem
The manual creation of software code optimized for specific hardware architectures is time-consuming and error-prone, and existing methods often fail to fully utilize the hardware and software capabilities of diverse processing architectures.
Innovation Solution
A method and system for automatically generating architecture-specific algorithms using dynamically reconfigurable computing blocks, which are associated with simulation and execution codes, to ensure compliance with algorithm parameters and optimize execution on target processing architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual code creation is used to optimize software for specific hardware architectures, then the code can be tailored to hardware capabilities, but the process becomes time-consuming and error-prone
Solution Approach 1:
The system performs preliminary analysis of hardware architecture capabilities and pre-generates optimized code through automated compilation. The compiler analyzes the target hardware architecture in advance, selects appropriate optimization strategies, and generates optimized code automatically, eliminating the need for time-consuming manual optimization while maintaining high code quality
Solution Approach 2:
The patent replaces the mechanical manual process of code optimization with an automated computer-based compilation system. The compiler automatically analyzes source code, determines optimal execution strategies based on hardware capabilities, and generates optimized machine code without human intervention, thereby reducing both time and errors
2Ease of manufacture
If existing code generation methods are used, then development is simpler, but hardware and software capabilities of diverse processing architectures are not fully utilized
Solution Approach 1:
The compiler dynamically adjusts compilation parameters and optimization strategies based on the specific hardware architecture being targeted. By analyzing hardware capabilities such as processor type, memory hierarchy, and instruction set, the system automatically modifies code generation parameters to fully utilize the target hardware's potential while maintaining ease of use through automated processes
Solution Approach 2:
The patent creates a universal compilation system that can adapt to multiple diverse processing architectures through a single automated toolchain. The compiler is designed to recognize and optimize for various hardware platforms, providing both ease of use and broad hardware capability utilization through its multi-functional architecture
Data Source
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AI summary
A method of generating automatically architecture-specific algorithms, comprising receiving an architecture independent algorithm and one or more algorithm parameters defining at least a target processing architecture and a format of an output of an architecture-specific algorithm implementing the received algorithm, determining automatically a functionality of the algorithm by analyzing the algorithm, selecting one or more architecture-specific computing blocks of the target processing architecture according to the functionality of the algorithm and the algorithm parameter(s) wherein each computing block is dynamically reconfigurable in runtime and associated with (1) simulation code simulating its functionality, and (2) execution code executing its functionality, testing an emulated architecture-specific algorithm constructed using the simulation code of the selected architecture-specific computing block(s) to verify compliance with the algorithm parameter(s), and, responsive to successful compliance verification, generating automatically an architecture-specific code segment implementing the architecture-specific algorithm based on the execution code of the selected architecture-specific computing blocks.