Arcuate Control Gate for Flash Memory Short Channel Effect
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Solution Overview
Problem
The short channel effect in two-bit flash memory cells reduces the controllability of the control gate, leading to an insufficient memory cell window, particularly in the 60 nm generation semiconductor manufacturing process.
Innovation Solution
An arcuate-shaped control gate is formed with additional gate portions near the channel region, and isolation structures are used to enhance the controllability of the control gate, with a dielectric layer sandwiched between the control gate and floating gates, and an insulating layer between the floating gates and the substrate, forming an oxide-nitride-oxide structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel length is shortened to cater to 60 nm generation manufacturing process, then the manufacturing precision is improved, but the controllability of the control gate deteriorates due to short channel effect
Solution Approach 1:
The control gate is transformed from a planar structure to a three-dimensional wraparound structure that extends along the sidewalls of the channel region. This dimensional change allows the control gate to exert influence from multiple spatial directions (top and sidewalls), effectively compensating for the reduced channel length and restoring controllability in scaled devices.
Solution Approach 2:
The control gate is divided into multiple segments: a first control gate portion covering the channel region and a second control gate portion extending along the sidewalls. This segmentation allows each portion to independently contribute to channel control, with the sidewall portion providing additional control leverage that compensates for short channel effects.
2Length of moving object
If the channel length is shortened, then the device scaling is improved, but the memory cell window becomes insufficient
Solution Approach 1:
By extending the control gate along the sidewalls of the channel region, the patent creates additional control pathways in the vertical dimension. This multi-directional control enhances the ability to modulate the channel, thereby improving the memory cell window (difference between programmed and erased states) even with shortened channel length.
Solution Approach 2:
The control gate structure is optimized locally at different positions: the first control gate portion provides top-down control over the channel region, while the second control gate portion provides lateral control along the sidewalls. This localized structural differentiation ensures effective electric field distribution throughout the shortened channel, maintaining sufficient memory cell window.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the controllability of the control gate and enhances the memory cell window, addressing the short channel effect and improving memory performance.
Implementation Method 1
a dielectric layer sandwiched by the control gate and each of the two floating gates... an insulating layer sandwiched by the two floating gates and the protrusion... forming an oxide-nitride-oxide structure
Data Source
AI summary
A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.