Area-Aware Test Pattern Grid Optimization for Semiconductor Defect Detection
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Solution Overview
Problem
As semiconductor devices become more densely packed, the time required to test them increases due to the generation of test patterns that do not consider the area or location of transistors, leading to inefficiencies and higher costs as extrinsic defects dominate at mature process nodes.
Innovation Solution
Implementing an area-aware optimization method that divides the chip area into a grid based on the smallest particle size, preparing and sorting test patterns to exercise all or a predetermined percentage of grid locations, allowing for rapid identification of extrinsic defects and reducing overall test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test pattern generation methods are used that exercise all transistors, then test coverage is improved, but test time increases significantly
Solution Approach 1:
The chip area is divided into a grid of subareas, and test patterns are segmented to cover specific grid locations. This segmentation allows the test system to focus on covering all grid locations rather than exercising every single transistor, thereby reducing test time while maintaining adequate coverage for detecting extrinsic defects.
Solution Approach 2:
The patent applies partial action by requiring test patterns to cover all grid locations rather than exercising every transistor. This partial coverage approach is sufficient to detect extrinsic defects (particle contaminants) without the excessive time cost of complete transistor-level exercise, thus resolving the contradiction between coverage and test time.
2Manufacturing precision
If more transistors are packed into the same footprint to increase density, then manufacturing precision is improved, but test time increases due to more transistors to cover
Solution Approach 1:
The patent shifts the testing approach from a transistor-level dimension to a spatial/grid dimension. By dividing the chip into grid locations and requiring coverage of all grid locations, the system efficiently tests high-density circuits without test time increasing proportionally with transistor count, thus accommodating increased manufacturing precision.
3Reliability
If comprehensive test patterns are generated to meet test coverage requirements, then reliability is improved, but productivity decreases due to longer test times
Solution Approach 1:
The test patterns are segmented to cover grid locations rather than all transistors. This segmentation enables faster testing that meets production requirements while maintaining sufficient coverage to detect extrinsic defects, thus improving productivity without sacrificing essential reliability.
Solution Approach 2:
The patent applies partial action by requiring coverage of all grid locations rather than complete transistor exercise. This partial coverage achieves the necessary reliability for detecting particle contaminants while significantly reducing test time, thereby improving production efficiency.
Data Source
AI summary
In some embodiments, a method may include an area-aware optimization for the test patterns. The method may include dividing the chip area into a grid. The grid may be based on the smallest particle size. The method may include preparing test patterns and identifying a subset of test patterns that touch all of the grid locations. The subset may include a minimum number of test patterns from the prepared test patterns which when implemented exercise the all of the grid locations. The method allows to more quickly determine chips that fail due to extrinsic defects. Once a test fails during the testing process for a chip, testing on the chip is stopped and testing begins on the next chip. Rapidly identifying chips that fail due to extrinsic failures can decrease the overall test time and identify those that will fail quickly as the chip process matures and is dominated by extrinsic failures.