Area-Efficient Subtractor Using Shared XNOR Gates
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Solution Overview
Problem
In integrated circuit design, the focus on minimizing timing delay often overlooks area-saving designs, leading to inefficiencies in functional blocks, particularly in non-critical data paths where slower logic designs can be used without affecting overall timing requirements.
Innovation Solution
The synthesis of an area-efficient subtractor functional block that uses optimized Boolean logic expressions and a ripple carry architecture to reduce the number of gates and transistors, allowing for the sharing of exclusive-NOR gates and conserving area without inverting all bits of the input vector, thereby enabling area savings and power conservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional fast subtractor designs are used to minimize timing delay, then speed is improved, but area consumption increases
Solution Approach 1:
The patent applies different design qualities to different parts of the subtractor based on timing criticality. Non-critical data path blocks use area-efficient designs with slower logic, while critical paths maintain fast logic. This local differentiation resolves the contradiction by optimizing area where speed requirements are relaxed.
Solution Approach 2:
The synthesis tool dynamically selects between fast and area-efficient subtractor designs based on timing analysis of each data path block. This dynamic adaptation allows the system to choose the appropriate design style (fast or area-efficient) for each specific location, resolving the speed-area tradeoff.
2Area of stationary object
If area-efficient subtractor designs are used to reduce area consumption, then area is improved, but timing delay increases
Solution Approach 1:
Area-efficient designs are selectively applied only to non-critical data path blocks where timing delay is not a constraint. This local application resolves the contradiction by allowing area optimization in regions where speed requirements are satisfied by other parts of the circuit.
Solution Approach 2:
The synthesis process dynamically determines which subtractor instances should use area-efficient designs based on timing analysis. This dynamic selection ensures that area optimization is applied only where it will not violate timing requirements, resolving the speed-area tradeoff.
3Reliability
If all bits of input vector are inverted in conventional subtractor designs, then subtraction functionality is achieved, but area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the unnecessary bit inversion operation from the subtractor design. By using a different logical approach that does not require inverting all input bits, the design achieves the same subtraction functionality with reduced area and power consumption.
Solution Approach 2:
Instead of inverting all bits of the input vector as in conventional designs, the patent uses an alternative approach that inverts fewer bits or uses different logic to achieve the same subtraction result, thereby reducing area and power consumption.
Data Source
AI summary
In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of the reduced full subtractor cell is replicated for all bits of the area-efficient subtractor but for the least significant bit. One of a plurality of netlists of subtractor cells is selected for the least significant bit of the area-efficient subtractor in response to a flex bit.