Area Efficient Traffic Generator for Network Monitoring
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Solution Overview
Problem
Existing network performance monitoring systems face challenges in implementing scalable traffic generator and inspector modules on small Field Programmable Gate-Arrays (FPGAs, which lack sufficient logic and memory, and require expensive Application Specific Integrated Circuits (ASICs) or large external memories, limiting flexibility and resource usage.
Innovation Solution
A packet generation and inspection system utilizing a processor-controlled arbiter and dual-port RAM to manage multiple flows simultaneously, with software-configurable instructions and data stored in memory, allowing for real-time packet generation and analysis without distributed memory, supporting flexible packet formats and behavior changes without modifying FPGA code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traffic generator and inspector modules are implemented on small FPGAs, then flexibility and scalability are improved, but resource availability (logic and memory) is insufficient
Solution Approach 1:
The patent divides the traffic generator and inspector functionalities into separate modular components that can be independently configured and executed on the FPGA. Each module handles specific packet processing tasks, allowing efficient utilization of limited FPGA resources while maintaining flexibility for different network monitoring scenarios.
Solution Approach 2:
The system implements universal packet processing modules that can handle multiple packet formats and inspection types through software configuration rather than dedicated hardware for each function. This multi-functionality approach allows the same hardware resources to serve multiple purposes, increasing adaptability without requiring additional physical resources.
2Quantity of substance
If ASICs are used instead of FPGAs, then resource sufficiency is improved, but cost and flexibility deteriorate
Solution Approach 1:
The patent employs dynamically reconfigurable logic within the FPGA that can be programmed to implement different packet processing algorithms and inspection rules. This dynamic capability allows the system to adapt to changing network monitoring requirements without requiring new hardware design, providing ASIC-like resource efficiency while maintaining FPGA reconfigurability and lower cost.
3Quantity of substance
If distributed memory is used, then memory capacity is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the packet buffer and processing logic into a unified memory structure that is shared across all packet processing modules. This centralized memory approach eliminates the need for separate distributed memory modules, reducing overall device complexity while providing sufficient memory capacity for packet buffering and processing operations.
Data Source
AI summary
A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.