Areal Interconnect Transistor Package for Low-Resistance Current Paths
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in providing high routing capability, variability of footprint design, board level reliability, thermal dissipation, and low assembly cost, particularly for wide band gap applications like GaN or SiC, where short and low resistance current paths are needed to minimize power loss and maximize performance.
Innovation Solution
A semiconductor chip package design featuring an interconnect substrate with a first metal layer having a pattern of holes and a second metal layer with protrusions passing through the holes, connected to load current chip pads, optimizing current paths and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional packaging techniques are used, then assembly cost and manufacturing simplicity are maintained, but electrical resistance increases and current path efficiency deteriorates
Solution Approach 1:
The patent transitions from planar interconnect routing to a three-dimensional stacked architecture with multiple metal layers (first metal layer, second metal layer) connected via vertical vias. This dimensional change enables current to flow through multiple layers in parallel, increasing the effective conductive cross-section and reducing electrical resistance without increasing the chip footprint area.
Solution Approach 2:
The interconnect structure is segmented into multiple functional metal layers separated by insulating material. The first metal layer handles certain current paths while the second metal layer handles others, with vias providing vertical interconnections. This segmentation allows independent optimization of each layer's routing and reduces current crowding effects.
2Reliability
If longer current paths are used for routing, then routing capability and footprint variability improve, but electrical resistance increases
Solution Approach 1:
The patent utilizes vertical vias to create three-dimensional current paths that bypass the limitations of planar routing. By stacking metal layers and connecting them through vias, the design achieves both short current paths (reducing resistance) and flexible routing capability (improving board level reliability) simultaneously.
Solution Approach 2:
Multiple current paths through different metal layers are merged into parallel conductive channels. The first and second metal layers work together to provide redundant and parallel current flow paths, reducing overall electrical resistance while maintaining routing flexibility for board level reliability.
3Loss of energy
If thicker metal layers are used, then electrical resistance decreases, but manufacturing complexity and assembly difficulty increase
Solution Approach 1:
Instead of using a single thick metal layer that would be difficult to manufacture, the patent segments the conductive path into multiple thinner metal layers connected by vias. Each layer can be manufactured using standard thin-film deposition processes, and the vias provide vertical interconnection, achieving the equivalent of a thick conductor through parallel paths.
Solution Approach 2:
The patent distributes the required conductive cross-section across multiple vertical layers rather than concentrating it in a single horizontal layer. This dimensional distribution enables the use of standard thin-film manufacturing processes while achieving low overall resistance through the combined parallel paths of multiple layers.
Data Source
AI summary
A semiconductor chip package includes a semiconductor transistor chip having a first side and a second side opposite the first side. The first side includes first load current chip pads and second load current chip pads. An interconnect substrate includes a first metal layer, a second metal layer, and an insulating material disposed between the first metal layer and the second metal layer. The first metal layer includes a pattern of holes, the second metal layer includes a pattern of protrusions, and the protrusions pass through the holes. The semiconductor transistor chip is mounted on the interconnect substrate with the first side facing the interconnect substrate. The first metal layer is connected to a plurality of the first load current chip pads and the second metal layer is connected via the pattern of protrusions to a plurality of the second load current chip pads.