Areal Internal Interconnect for Low-Resistance Transistor Packaging
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in providing high routing capability, variability of footprint design, board level reliability, thermal dissipation, and low assembly cost, especially for wide band gap applications like GaN or SiC, which require very short and low resistance current paths.
Innovation Solution
A semiconductor chip package design featuring an interconnect substrate with a first metal layer having a pattern of holes and a second metal layer with protrusions passing through these holes, connected to load current chip pads, optimizing current paths and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional packaging techniques are used, then assembly cost and manufacturing simplicity are maintained, but electrical resistance increases and current transport efficiency decreases
Solution Approach 1:
The patent transitions from planar two-dimensional interconnect routing to three-dimensional stacked metal layers. Multiple metal layers (first metal layer, second metal layer, third metal layer) are stacked vertically with via holes connecting them, creating areal internal interconnect paths that reduce current path length and resistance while maintaining a compact footprint.
Solution Approach 2:
The interconnect structure is segmented into multiple functional metal layers: first metal layer for source/drain connections, second metal layer for intermediate routing, and third metal layer for final pad connections. This segmentation allows optimized current paths through via holes and reduces overall electrical resistance by distributing current across multiple conductive paths.
2Length of moving object
If short current paths are implemented, then electrical resistance decreases, but packaging complexity increases
Solution Approach 1:
The patent uses vertical stacking of metal layers to create short areal interconnect paths. The first metal layer is positioned adjacent to the chip, the second metal layer is stacked above it with via holes providing vertical connections, and the third metal layer provides additional routing. This three-dimensional arrangement minimizes current path length compared to conventional planar routing while managing the increased structural complexity through systematic layering.
3Adaptability or versatility
If multiple metal layers are used, then routing capability increases, but manufacturing complexity increases
Solution Approach 1:
The interconnect substrate is pre-assembled with multiple metal layers, via holes, and insulating materials before chip mounting. The first metal layer, second metal layer, and third metal layer are prepared in advance with appropriate via hole patterns and connection points. This preliminary preparation of the interconnect substrate simplifies the final assembly process by reducing on-site manufacturing steps while maintaining high routing capability.
Solution Approach 2:
The multi-layer metal structure serves multiple functions: electrical interconnection, signal routing, and thermal management. The same stacked metal layers that provide areal interconnect paths also function as heat dissipation pathways, combining multiple functions into a single structural solution that reduces overall packaging complexity.
Data Source
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AI summary
A semiconductor chip package includes a semiconductor transistor chip having a first side and a second side opposite the first side. The first side includes first load current chip pads and second load current chip pads. An interconnect substrate comprises a first metal layer, a second metal layer and an insulating material disposed between the first metal layer and the second metal layer. The first metal layer includes a pattern of holes, the second metal layer includes a pattern of protrusions, and the protrusions pass through the holes. The semiconductor transistor chip is mounted on the interconnect substrate with the first side facing the interconnect substrate. The first metal layer is connected to a plurality of the first load current chip pads and the second metal layer is connected via the pattern of protrusions to a plurality of the second load current chip pads.