32-bit Instruction Extension for ARIA Encryption on IoT Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current technologies face challenges in implementing efficient block cipher algorithms like ARIA on low-performance processors, particularly in IoT devices, due to the need for high-performance computational abilities and the difficulty of adding instructions that require hardware structure changes, limiting their application to high-performance processors.
Innovation Solution
A hardware module with a 32-bit instruction extension for processors that supports ARIA encryption and decryption operations, enabling 128-bit operations using 32-bit unit instructions, including substitution and diffusion layer instructions, to enhance performance on low-performance processors like lightweight IoT devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 128-bit unit instructions are added for block cipher AES (AES-NI), then encryption/decryption performance is improved, but device complexity increases and it cannot be applied to low-performance processors
Solution Approach 1:
The patent segments the 128-bit block cipher operation into four separate 32-bit instruction operations. Each 32-bit instruction handles a portion of the encryption/decryption process, allowing low-performance processors to execute the full 128-bit ARIA algorithm through sequential 32-bit operations rather than requiring a single complex 128-bit instruction unit.
Solution Approach 2:
The patent changes the operational parameter from 128-bit unit instructions to 32-bit unit instructions. This parameter change allows the crypto module to be implemented with smaller, simpler hardware structures that can be deployed on low-performance processors while still achieving the required 128-bit encryption/decryption functionality through multiple 32-bit operations.
2Reliability
If crypto algorithm instructions are added to strengthen security, then security is improved, but hardware structure changes are required which increases device complexity
Solution Approach 1:
The patent divides the security-enhancing crypto operations into segmented 32-bit instructions that can be processed by existing low-performance processor architectures. This segmentation allows security functionality to be added without requiring fundamental hardware structure changes, as each segment can be handled by simple, resource-efficient circuitry.
Solution Approach 2:
The patent creates a universal 32-bit instruction set that can handle multiple crypto operations (substitution layer, diffusion layer, key generation) within a unified hardware module. This multi-functionality allows a single simplified hardware structure to provide comprehensive security capabilities without requiring separate dedicated circuits for each operation.
3Productivity
If large operation units are used for crypto instructions, then encryption/decryption capability is improved, but the size of the crypto module increases making it unsuitable for low-performance processors
Solution Approach 1:
The patent segments the large 128-bit operation unit into four smaller 32-bit operation units. Each unit processes a 32-bit portion of the data, reducing the area required for each individual operation unit while maintaining the overall 128-bit encryption/decryption capability through sequential processing of the segmented data blocks.
Data Source
AI summary
Disclosed is a hardware module with a 32-bit unit operation for processor supporting ARIA encryption and decryption, including: an instruction pipeline that executes an instruction fetch, instruction decoding, and an instruction execution; and an ARIA operation module that has a 32-bit unit operation system provided in the instruction execution pipeline to support ARIA encryption and decryption. Two types of instructions, ARIA substitution layer and diffusion layer instructions are provided as a 32-bit unit operation instruction in order to provide an ARIA encryption/decryption function through the ARIA operation module, the substitution layer instruction includes two instructions for an even round and an odd round of the ARIA encryption/decryption, and the diffusion layer includes four types of diffusion layer instructions for the even sub-round and four types of diffusion layer instructions for the odd sub-round.