Arithmetic Bitwise Unit Conditional Statement Execution

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Solution Overview

Problem

The execution of conditional statements in computing systems is bottlenecked by digital comparators, which require at least 2 clock cycles per operation and cannot perform parallel execution of multilevel conditional tasks, limiting processor efficiency.

Innovation Solution

Transforming conditional statements into arithmetic and/or bitwise operations, allowing their execution solely by the arithmetic and/or bitwise units of the processor without a digital comparator, enabling faster execution and parallel processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a digital comparator is used to evaluate Boolean conditions, then conditional statements can be executed, but the execution speed is limited to at least 2 clock cycles per operation

Engineering Contradiction:
Improveexecution speedVSAvoidclock cycles per operation
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent replaces the digital comparator (mechanical/electronic comparison system) with an arithmetic unit that performs conditional evaluation through arithmetic operations. Instead of using dedicated comparison hardware that takes 2+ clock cycles, the system uses arithmetic operations (subtraction, multiplication, division) that can complete in 1 clock cycle, thereby increasing execution speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational parameters by transforming Boolean condition evaluation from a dedicated comparison function into arithmetic operations. By representing conditions as arithmetic expressions (e.g., converting 'a > b' into arithmetic comparisons), the system achieves faster execution by leveraging the 1-clock-cycle capability of arithmetic units rather than being constrained by the 2-clock-cycle minimum of comparator operations.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If a digital comparator is used for conditional evaluation, then Boolean conditions can be assessed, but parallel execution of multilevel conditional tasks is not possible

Engineering Contradiction:
Improveparallel execution capabilityVSAvoidmultilevel conditional task execution
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments multilevel conditional tasks into independent arithmetic operations that can be executed in parallel. Instead of processing conditions sequentially through a single comparator, the system divides complex conditional logic into multiple arithmetic expressions that can be evaluated simultaneously by multiple arithmetic units, enabling parallel execution and improving productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent makes the arithmetic unit universal by enabling it to perform both arithmetic calculations and conditional evaluations. The same arithmetic unit that handles mathematical operations also evaluates Boolean conditions through arithmetic expressions, allowing a single unit to serve multiple functions and enabling parallel processing of multilevel conditional tasks.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If a digital comparator is used in the processor, then conditional statements can be executed, but the comparator constitutes a bottleneck limiting overall processor efficiency

Engineering Contradiction:
Improveprocessor efficiencyVSAvoidprocessor architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the conditional evaluation function from the digital comparator and integrates it into the arithmetic unit. By removing the dependency on separate comparator hardware and embedding conditional logic within arithmetic operations, the system eliminates the bottleneck and improves processor efficiency without adding complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the conditional evaluation function with the arithmetic unit, combining what were previously separate functions (comparison and arithmetic operations) into a single integrated unit. This consolidation eliminates the bottleneck created by separate comparator hardware and improves overall processor efficiency by reducing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4058885B1Execution of a conditional statement by an arithmetic and/or bitwise unit
Publication Date: 2024.05.01 CHARIOT TECHNOLOGIES LAB INC
  • EP4058885B1 patent drawingFigure 1
  • EP4058885B1 patent drawingFigure 2
  • EP4058885B1 patent drawingFigure 3

AI summary

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for execution of a conditional statement by an arithmetic and/or bitwise unit. A computer program that comprises a conditional statement that comprises a Boolean condition is accessed. The Boolean condition is transformed into an arithmetic and/or bitwise expression of the Boolean condition. An arithmetic and/or bitwise expression of the computer program comprises the arithmetic and/or bitwise expression of the Boolean condition in place of the Boolean condition. The arithmetic and/or bitwise expression of the computer program is executed by an arithmetic and/or bitwise operation unit of a processor.