Arithmetic Branch Fusion via Micro-operation Merging
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Solution Overview
Problem
Modern processors struggle to fuse arithmetic and branch instructions that do not use architectural flags for decision-making, limiting processing efficiency in certain instruction set architectures.
Innovation Solution
A processor is configured to detect arithmetic instructions followed by branch instructions that change program flow based on the result of the arithmetic instruction, allowing these instructions to be fused into a single micro-operation for execution in one cycle, using a fusion detect unit and merge logic to combine their execution information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If branch fusion is performed using architectural flags, then execution cycles are reduced, but it cannot be applied to branch instructions that do not use architectural flags
Solution Approach 1:
The patent merges arithmetic instructions with branch instructions into a single micro-operation, combining their execution information and control logic. This allows the branch decision to be made based on arithmetic results without waiting for architectural flag updates, enabling fusion for branch instructions that traditionally did not support flag-based fusion.
Solution Approach 2:
The patent introduces an intermediary mechanism that captures arithmetic results before they are written to architectural flags. This intermediary allows the branch instruction to access the arithmetic result directly, enabling branch fusion without relying on the traditional flag update sequence.
2Productivity
If arithmetic and branch instructions are executed separately, then instruction decoding is simple, but processing efficiency is reduced
Solution Approach 1:
The decode unit merges arithmetic and branch instructions into a single micro-operation with combined execution information. This allows both instructions to be decoded and prepared in advance, improving processing efficiency by eliminating the need to wait for separate instruction execution cycles.
Solution Approach 2:
The patent implements preliminary decoding and preparation of both arithmetic and branch instructions before execution. The execution information for both instructions is captured and prepared in advance, allowing them to be executed together in a single cycle without requiring complex real-time decoding.
Data Source
AI summary
A processor and method for fusing together an arithmetic instruction and a branch instruction. The processor includes an instruction fetch unit configured to fetch instructions. The processor may also include an instruction decode unit that may be configured to decode the fetched instructions into micro-operations for execution by an execution unit. The decode unit may be configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction. In addition, the processor may further be configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed. The single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction.