Arithmetic Processing Device Bypass Paths for Trig Function Efficiency

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Solution Overview

Problem

The existing arithmetic processing devices face a reduction in processing efficiency due to the need to execute multiply-add operations for Taylor series expansions of trigonometric functions only after completing auxiliary instructions, leading to inefficiencies in trigonometric function calculations.

Innovation Solution

The proposed arithmetic processing device includes a register file, coefficient memory, multiply-add arithmetic unit, multiplexers, OR circuits, and EOR circuits that allow for the calculation of trigonometric functions sin(x) and cos(x) by pre-processing expansion point identification data and using bypass paths to optimize the execution of auxiliary instructions and multiply-add operations, enabling efficient calculation of trigonometric functions without waiting for auxiliary instructions to complete.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If auxiliary instructions are executed before multiply-add operations for Taylor series expansion, then the trigonometric function calculation can be performed, but processing efficiency is reduced due to sequential execution

Engineering Contradiction:
Improvecorrectness of trigonometric function calculationVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent pre-calculates and stores expansion point identification data (bxq) and coefficient data in bypass memory before the main calculation flow requires them. This preliminary action allows the multiply-add unit to immediately access pre-prepared data without waiting for auxiliary instructions to complete, thereby resolving the contradiction between calculation correctness and processing efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces bypass memory as an intermediary component that stores pre-calculated expansion point identification data and coefficients. This intermediary allows the main calculation path to proceed independently of the auxiliary instruction completion, enabling parallel execution and improving processing efficiency while maintaining calculation correctness

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If auxiliary instructions are completed before executing multiply-add operations, then calculation accuracy is ensured, but processing time increases due to sequential execution

Engineering Contradiction:
Improvecalculation accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The expansion point identification data (bxq) and coefficient data are pre-calculated and stored in bypass memory before the multiply-add operations begin. This preliminary preparation ensures that accurate data is readily available when needed, maintaining calculation accuracy while eliminating the time loss associated with sequential execution

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous execution by allowing the multiply-add unit to operate continuously with pre-prepared data from bypass memory, rather than pausing to wait for auxiliary instructions. This continuity maintains calculation accuracy through proper data preparation while significantly reducing processing time

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10824395B2Arithmetic processing device and control method for arithmetic processing device
Publication Date: 2020.11.03 FUJITSU LTD
  • US10824395B2 patent drawing
  • US10824395B2 patent drawing
  • US10824395B2 patent drawing

AI summary

An arithmetic processing device includes a coefficient memory storing coefficients of a Taylor series expansion of a trigonometric function, a multiply-add arithmetic unit, a first bypass path supplying an output of the multiply-add arithmetic unit to a register file, an OR circuit calculating OR of a sign bit of the output of the multiply-add arithmetic unit and a least significant bit of a second input, a first selector selecting either a first input y or a value “1.0” an EOR circuit calculating an EOR of a first bit of the second input and a sign bit of an output of the first selector, and a second bypass path supplying the least significant bit of the second input to a coefficient selector. The multiply-add arithmetic unit executes an auxiliary instruction repeatedly while modifying a coefficient index from a maximum value to a minimum value to calculate sin (x).