Reconfigurable Arithmetic Circuit with Scalable Core Pairing
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Solution Overview
Problem
Existing computing systems face limitations in processing speed and energy efficiency for mathematically intensive applications such as artificial intelligence, neural networks, digital currencies, and blockchain, with a need for scalable, low-latency, and energy-efficient solutions capable of real-time processing and massive parallel processing.
Innovation Solution
A reconfigurable arithmetic engine circuit with a scalable architecture that includes input reordering queues, a multiplier shifter and combiner network, an accumulator circuit, and control logic, allowing for various operating modes and interconnection networks to optimize hardware for specific applications, enabling high-performance and energy-efficient processing across multiple cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing computing systems are used for mathematically intensive applications, then computation processing is performed, but the speed of computation is insufficient and energy consumption is excessive
Solution Approach 1:
The computing system is divided into multiple independent computational cores that can operate in parallel. Each core is a self-contained unit capable of performing mathematical operations independently, allowing the system to process multiple tasks simultaneously and improve overall computation speed while distributing energy consumption across multiple units.
Solution Approach 2:
The computational cores are designed to be reconfigurable, allowing their functionality to be dynamically changed based on the specific application requirements. This enables the hardware to be optimized for different mathematically intensive tasks such as neural network computations, digital currency processing, blockchain operations, encryption/decryption, and Fast Fourier Transforms, thereby improving computation speed for specific workloads while maintaining energy efficiency.
2Productivity
If computational cores are increased to provide massive parallel processing, then processing capability is improved, but device complexity increases
Solution Approach 1:
Each computational core is designed as a universal unit that can perform multiple types of mathematical operations including neural network computations, digital currency processing, blockchain operations, encryption and decryption, and Fast Fourier Transforms. This multi-functionality allows a relatively small number of cores to provide massive parallel processing capability across diverse applications without requiring specialized hardware for each task, thereby reducing overall system complexity.
Solution Approach 2:
The computational cores utilize different numerical precision formats including 32-bit single precision, 16-bit half precision, and 8-bit quarter precision arithmetic. By allowing dynamic selection of precision levels based on application requirements, the system can optimize the balance between computation speed, accuracy, and resource utilization, enabling massive parallel processing with controlled complexity.
Data Source
AI summary
A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.