Arithmetic Circuit for Faster Galois Field ECC Multiplication
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Solution Overview
Problem
The calculation of error locator polynomials in error correction codes for non-volatile memory systems, such as NAND flash memory, involves multiple multiplications of Galois fields, leading to increased calculation time and circuit size.
Innovation Solution
An arithmetic circuitry is designed to perform arithmetic operations using AND and XOR operations, optimizing the calculation of Galois field multiplications by sharing computations and reducing the number of steps required for multiple multiplications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple multiplications of Galois field are performed in series for error correction decoding, then the accuracy of error correction is improved, but the calculation time increases
Solution Approach 1:
The patent combines multiple Galois field multiplication operations into a unified computational framework using tensor representations. By merging p multiplications into a single tensor contraction operation, the system maintains error correction accuracy while reducing the sequential calculation time required for multiple individual multiplications.
Solution Approach 2:
The patent transforms traditional scalar or vector-based Galois field multiplications into tensor-based operations, adding dimensional complexity to the computational approach. This dimensionality change allows multiple multiplications to be represented and executed more efficiently through tensor contractions, reducing the overall calculation time while preserving accuracy.
2Reliability
If multiple multiplications of Galois field are performed in series for error correction decoding, then the accuracy of error correction is improved, but the circuit size increases
Solution Approach 1:
The patent merges multiple separate multiplication circuits into a single integrated tensor contraction unit. By combining p individual Galois field multiplication operations into one unified tensor-based computational block, the system achieves the required error correction accuracy while significantly reducing the overall circuit size and component count.
Solution Approach 2:
The tensor contraction unit serves as a universal computational block that can perform multiple Galois field multiplication operations simultaneously. This multi-functional approach allows a single circuit element to replace multiple specialized multiplication circuits, reducing device complexity while maintaining the ability to perform all necessary error correction calculations.
3Measurement precision
If p multiplications are performed in series using traditional methods, then the result is accurate, but the number of computational steps increases
Solution Approach 1:
The patent introduces tensor algebra as a higher-dimensional mathematical framework to represent and execute Galois field multiplications. By lifting the operations from traditional scalar/vector arithmetic into tensor space, the system can compute p multiplications through a single contraction operation, maintaining precision while dramatically improving computational efficiency and reducing the number of discrete steps required.
Data Source
AI summary
Arithmetic circuitry according one embodiment performs a first arithmetic operation by AND operations and XOR operations. The first arithmetic operation corresponds to p multiplications (p is an integer of 2 or more) to be performed in series. The p multiplications are respectively represented by p order-3 tensors each receiving two elements of a Galois field as inputs and outputting one element as a result of multiplication of the two elements. The AND operations calculate AND values of a plurality of elements used in the p multiplications. The XOR operations are based on a contracted tensor obtained by contraction of an order-3p tensor obtained by a direct product of the p order-3 tensors and the AND values.