Arithmetic Circuit Layout for Fast Multiplication and Division
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Solution Overview
Problem
Existing arithmetic devices face a tradeoff between area occupancy and operation speed when performing multiplication and division, with current solutions either consuming excessive area for high-speed operations or failing to meet time limits due to insufficient clock edges.
Innovation Solution
The proposed arithmetic device employs a configuration with multiple arithmetic devices and a selective conversion circuit to perform multiplication using control signals, allowing for efficient multiplication with a small area and reduced error rates, while also enabling division operations by approximating fractional multipliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large number of adders/subtractors are arranged to perform arithmetic operations in parallel, then operation speed is improved, but area occupied by the arithmetic device increases
Solution Approach 1:
The arithmetic device is divided into multiple functional units including a first arithmetic unit for multiplication, a second arithmetic unit for division, and a selective conversion circuit. Each unit handles specific operations independently, allowing parallel processing while maintaining compact individual unit sizes, thus achieving high speed without excessive area occupation.
Solution Approach 2:
The arithmetic device is designed to perform multiple functions (multiplication and division) using shared resources and control mechanisms. The selective conversion circuit enables the same hardware structure to switch between different arithmetic operations, reducing the need for separate dedicated circuits for each operation and thereby minimizing area while maintaining operational speed.
2Area of stationary object
If the arithmetic device area is reduced, then area occupancy is improved, but operation speed decreases and time limits are not met
Solution Approach 1:
The arithmetic device employs dynamic control signals to switch between different operational modes (multiplication, division, selective conversion) in real-time. This dynamic reconfiguration allows the compact device to adapt its internal data flow and processing paths based on the current operation requirements, maximizing the utilization of limited hardware resources and maintaining high operation speed despite reduced area.
Solution Approach 2:
The device includes preliminary conversion circuits that prepare data in advance for subsequent arithmetic operations. By performing selective conversion and data preparation before the main arithmetic operations, the device optimizes the input data format and reduces the complexity of the main processing units, enabling faster execution within a compact area.
3Ease of manufacture
If conventional multiplication methods are used, then implementation is simple, but error rates increase and precision is reduced
Solution Approach 1:
The selective conversion circuit acts as an intermediary between the input data and the arithmetic units. It converts input data into optimized formats that reduce rounding errors and precision loss during arithmetic operations. This intermediate conversion step maintains implementation simplicity while significantly improving calculation precision and reducing error rates.
Data Source
AI summary
According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.