Arithmetic Circuit ID Routing for Electronic Computer Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic computer configurations that utilize multiple arithmetic units as accelerators, data transfer from the control unit to these units becomes a bottleneck, limiting throughput improvement.
Innovation Solution
The implementation of a system where each arithmetic circuit is assigned a unique ID, allowing direct data transmission and reception between them, reducing the need for control unit-mediated data transfers and enhancing throughput by enabling sequential execution of processing tasks across multiple arithmetic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed through the control unit to arithmetic parts, then the control unit can manage processing tasks, but the data transfer becomes a bottleneck and throughput is limited
Solution Approach 1:
The patent segments the data transfer path by introducing intermediate arithmetic circuits between the control unit and final arithmetic parts. Instead of direct control-unit-to-arithmetic-part transfers, data flows through multiple stages: control unit → first arithmetic circuit → second arithmetic circuit → target arithmetic part. This segmentation distributes the transfer burden and reduces the bottleneck effect at any single point.
Solution Approach 2:
The patent introduces intermediate arithmetic circuits as mediators in the data transfer path. These intermediate circuits receive data from the control unit, process or route it through arithmetic circuit IDs, and deliver it to the target arithmetic parts. This intermediary layer eliminates the direct bottleneck by creating buffer zones and alternative transfer paths.
2Adaptability or versatility
If multiple arithmetic parts are connected through a bus to the control unit, then various functions can be executed, but the bus becomes a congestion point and processing speed is reduced
Solution Approach 1:
The patent adds a new dimension to the data transfer architecture by introducing arithmetic circuit IDs as an additional routing parameter. Instead of relying solely on the bus topology for data transmission, the system uses arithmetic circuit IDs to create parallel, identifier-based transfer paths. This dimensional addition allows multiple data streams to be distinguished and routed independently, reducing bus congestion.
Solution Approach 2:
The patent segments the bus-based communication into multiple parallel transfer paths by using arithmetic circuit IDs as destinations. Data can be transferred to different arithmetic circuits simultaneously through different ID-based routes, effectively dividing the single-bus bottleneck into multiple parallel channels, thereby increasing overall data transfer speed while maintaining processing flexibility.
3Extent of automation
If the control unit mediates all data transfers to arithmetic parts, then centralized control is maintained, but the control unit becomes a bottleneck and processing throughput is limited
Solution Approach 1:
The patent introduces intermediate arithmetic circuits as automated intermediaries that handle data transfer and routing without requiring continuous control unit intervention. These intermediaries use arithmetic circuit IDs to automatically direct data to the correct target arithmetic parts, maintaining centralized control logic while eliminating the control unit as a bottleneck for actual data transfer operations.
Solution Approach 2:
The patent enables the arithmetic circuit system to perform self-routing and self-orchestration using arithmetic circuit IDs. Once data is introduced into the system, the intermediate arithmetic circuits automatically manage the transfer process by reading and acting on the arithmetic circuit ID information, reducing the control unit's direct involvement in data transfer operations and thereby increasing overall throughput.
Data Source
AI summary
An embodiment is an electronic computer including a plurality of arithmetic circuits which sequentially execute a plurality of processings on a processing data, and a controller which executes a program and performs a control of causing the plurality of arithmetic circuits to sequentially execute the plurality of processings. An arithmetic circuit ID is imparted to each of the plurality of arithmetic circuits, the plurality of arithmetic circuits include a first arithmetic circuit that executes a first processing among the plurality of processings, and a second arithmetic circuit that executes a second processing that executes processing on a processing result of the first processing among the plurality of processings, and the first arithmetic circuit transmits the processing result of the first processing to the arithmetic circuit ID of the second arithmetic circuit as a destination.