Arithmetic Circuit With Low Off-State Transistors for Data Retention
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Solution Overview
Problem
Conventional arithmetic circuits face high power consumption and large circuit area due to the need for separate nonvolatile storage and volatile storage means, leading to inefficiencies in data retention and processing.
Innovation Solution
An arithmetic circuit is designed with field-effect transistors having low off-state current, allowing data to be stored by controlling the potential of output signals using transistors that maintain data without the need for additional storage capacitors, thereby reducing power consumption and circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate nonvolatile storage circuit is used to save data, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The patent merges the storage function directly into the arithmetic circuit by using the arithmetic circuit's own nodes to hold data. The arithmetic circuit includes nodes that can maintain data states without requiring separate storage elements, thereby combining computation and storage functions in a single integrated structure that reduces power consumption while maintaining data retention reliability.
2Reliability
If separate nonvolatile storage circuit is used to save data, then data retention reliability is improved, but circuit area increases
Solution Approach 1:
The patent merges the storage function directly into the arithmetic circuit by using the arithmetic circuit's own nodes to hold data. The arithmetic circuit includes nodes that can maintain data states without requiring separate storage elements, thereby combining computation and storage functions in a single integrated structure that reduces circuit area while maintaining data retention reliability.
3Reliability
If conventional storage means is used, then data can be stored, but number of elements increases
Solution Approach 1:
The patent merges the storage function directly into the arithmetic circuit by using the arithmetic circuit's own nodes to hold data. The arithmetic circuit includes nodes that can maintain data states without requiring separate storage elements, thereby combining computation and storage functions in a single integrated structure that reduces the number of elements while maintaining data storage capability.
4Ease of operation
If data is transferred through data bus between arithmetic circuit and storage circuit, then data can be transferred, but power consumption increases
Solution Approach 1:
The patent extracts the storage function from separate storage circuits and integrates it directly into the arithmetic circuit structure. By using the arithmetic circuit's internal nodes to hold data, the need for data transfer through external data buses is eliminated, thereby reducing power consumption while maintaining data transfer capability within the integrated circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient data retention with reduced power consumption and smaller circuit area, eliminating the need for separate storage means and enhancing operation speed.
Implementation Method 1
a field-effect transistor with low off-state current is used as each of the first and second transistors
Implementation Method 2
an off-state current per micrometer of channel width of each of the first and second field-effect transistors is lower than or equal to 10 aA
Data Source
AI summary
In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.


