Arithmetic Circuit Pipelining Flip-Flop Reduction
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Solution Overview
Problem
Arithmetic circuits for neural processing units require a large number of flip-flops due to pipelining methods, leading to increased chip size and power consumption, especially in machine learning applications that rely heavily on multiply-accumulate operations.
Innovation Solution
The proposed arithmetic circuit design includes an input buffer, a first and second ripple carry adder, a flip-flop for carrying operations, and output buffers that latch and output sum signals, with flip-flops only added to the critical path, bypassing the feedforward-cutset rule, allowing for efficient pipelining without unnecessary flip-flop insertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining method is used for arithmetic circuit design, then processing speed is improved, but the number of flip-flops increases leading to larger chip size and higher power consumption
Solution Approach 1:
The patent extracts and removes unnecessary flip-flops from the pipelining structure by identifying and eliminating redundant latching points that do not contribute to the critical path, thereby reducing chip size while preserving essential pipeline functionality
Solution Approach 2:
The arithmetic circuit is segmented into functional blocks (multiplier, adder, accumulator) with pipelining applied only where necessary for timing closure, rather than uniformly across the entire circuit, reducing the total number of flip-flops required
2Speed
If pipelining method is used for arithmetic circuit design, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent removes unnecessary flip-flops from the pipelining structure, directly reducing the number of clocked elements that consume dynamic power during each clock cycle, thereby lowering overall power consumption while maintaining essential pipeline operation
3Stability of the object's composition
If feedforward-cutset rule is followed for pipelining, then circuit stability is improved, but the number of flip-flops increases unnecessarily
Solution Approach 1:
The patent extracts and removes flip-flops that are inserted according to the feedforward-cutset rule but do not lie on the critical path, thereby reducing device complexity while maintaining circuit stability through selective pipelining only where timing requirements demand it
Solution Approach 2:
The patent applies dynamic pipelining strategy where flip-flops are strategically placed only in locations that affect the critical path timing, rather than statically applying the feedforward-cutset rule uniformly, allowing the pipeline structure to adapt to actual timing requirements and reduce unnecessary complexity
Data Source
AI summary
An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.