Arithmetic Processing Device Circuit Sharing Convolution and Full-Connect Layers
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Solution Overview
Problem
Existing arithmetic processing devices for deep learning using convolutional neural networks (CNNs) face challenges in optimizing processing and memory usage due to differing data units across layers, leading to inefficiencies in convolution and full-connect processing, and lack of efficient circuit sharing between these processes.
Innovation Solution
The development of an arithmetic processing device that shares an entire circuit for both convolution and full-connect processing, supports shortcut processing, and maintains high DRAM transfer efficiency by utilizing a configuration with a data storage memory manager, coefficient storage memory manager, and an arithmetic part that performs filter processing, cumulative addition, non-linear arithmetic, and pooling operations, with a controller managing these components to handle variable filter sizes and optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate circuits are used for convolution processing and full-connect processing, then processing functionality is complete, but device complexity increases and circuit sharing efficiency decreases
Solution Approach 1:
The patent implements a universal arithmetic processing circuit that can perform both convolution processing and full-connect processing by dynamically configuring connection patterns. The same physical circuit resources are reused for different processing modes through control signals that adjust the connection topology between input and output nodes, eliminating the need for separate dedicated circuits for each processing type.
Solution Approach 2:
The circuit employs dynamic reconfiguration capabilities where connection patterns between processing elements can be changed during operation. Control logic dynamically adjusts the circuit topology to match the required processing mode (convolution or full-connect), allowing the hardware to adapt its structure based on the computational task at hand without requiring multiple fixed circuits.
2Speed
If the circuit is optimized for specific filter sizes, then processing speed improves, but adaptability to variable filter sizes decreases
Solution Approach 1:
The arithmetic processing circuit incorporates dynamic filter size configuration capabilities through control signals that adjust the number of taps and connection patterns in real-time. The circuit can be reconfigured between different filter sizes (e.g., 3x3, 5x5, 7x7) without requiring physical hardware changes, maintaining high processing speed across variable filter dimensions through optimized data flow paths for each configuration.
Solution Approach 2:
The circuit utilizes parameter-based reconfiguration where key operational parameters such as filter size, number of channels, and connection density can be dynamically adjusted through control registers. By changing these parameters rather than the physical structure, the circuit maintains optimal performance across different processing requirements while adapting to variable filter sizes through software-controlled configuration.
3Ease of manufacture
If data units are standardized across all processing layers, then circuit design simplifies, but processing efficiency for layer-specific optimizations decreases
Solution Approach 1:
The patent divides the neural network processing into segmented stages with different data unit requirements. The circuit is organized into modular blocks that can handle different data formats (e.g., image data with spatial dimensions, feature maps, flattened vectors) at different processing stages. Each segment is optimized for its specific data type while maintaining compatibility with the overall processing pipeline through standardized interfaces.
Solution Approach 2:
Different portions of the circuit are designed with locally optimized data handling capabilities. The convolution layer processes data with spatial structure using 2D array configurations, while the full-connect layer processes flattened vectors using 1D array configurations. Each local circuit segment is tailored to the specific data unit requirements of its processing layer, maximizing processing efficiency without requiring complete standardization across the entire system.
Data Source
AI summary
An arithmetic part of an arithmetic processing device includes: a filter processing part that has a multiplier and a first adder and performs filter processing; a second adder that performs cumulative addition processing that cumulatively adds all of the results of the filter processing as executed in N parallel; a non-linear conversion part that performs non-linear arithmetic processing on the result of the cumulative addition processing; a pooling processing part that performs pooling processing on the result of the non-linear arithmetic processing; and an arithmetic control part that controls the filter processing part, the second adder, the non-linear conversion part, and the pooling processing part.