Arithmetic Circuitry for Parallel Averaging Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital signal processing technologies lack efficient mechanisms for performing averaging arithmetic operations, particularly in video filtering, which are essential for processing and filtering digital signals effectively.
Innovation Solution
The development of an arithmetic circuitry within a digital signal processor (DSP) that includes averaging units capable of performing various averaging and summing operations on fixed-point values, allowing for efficient calculation of averages and sums of multiple values with or without rounding, utilizing a combination of adders and multiplexers to handle different input configurations in a single instruction cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional digital signal processing methods are used for averaging operations, then the processing can be performed, but the processing efficiency is low and multiple instruction cycles are required
Solution Approach 1:
The patent combines multiple averaging operations (average of two values, average of four values, average of eight values) and summing operations into a single arithmetic circuitry unit. This merging allows the processor to perform different averaging operations simultaneously using the same hardware resources, thereby improving processing efficiency and reducing the number of instruction cycles required.
Solution Approach 2:
The arithmetic circuitry is designed with universal functionality to handle multiple types of operations (averaging 2, 4, or 8 values, and summing operations) through a single unified structure. The circuit uses configurable parameters (N=2, 4, or 8) and selective activation of adder trees to perform different operations, making the hardware multi-functional and eliminating the need for separate dedicated circuits for each operation type.
2Speed
If dedicated hardware is designed for each specific averaging operation, then the operation speed is fast, but the device complexity increases
Solution Approach 1:
Instead of creating separate dedicated hardware circuits for averaging 2 values, 4 values, and 8 values, the patent implements a universal arithmetic circuitry that can be configured to perform any of these operations. The circuit uses a single adder tree structure with configurable depth and activation, allowing it to adapt to different N values (2, 4, or 8) without requiring separate hardware implementations for each case.
Solution Approach 2:
The arithmetic circuitry incorporates dynamic configurability through control signals that enable or disable specific adder stages based on the desired operation. When N=2, only the first adder stage is active; when N=4, the first two stages are active; when N=8, all three stages are active. This dynamic activation allows the same hardware to adapt its complexity to match the operational requirements, avoiding the need for permanently complex circuitry.
Data Source
AI summary
A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second inputs and a carry-in bit. An output of the first adder is coupled to a first input of the third adder, and an output of the second adder is coupled to a second input of the third adder. The arithmetic circuitry is able to calculate an arithmetic operation on a set of four inputs. The arithmetic operation is fully determined by control bits and may be: an average of two values (with or without rounding by 1), an average of four values (with or without rounding by 1 or 2), or a sum of four values.