Arithmetic and Control Unit for Parallel Processor Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The portability of user codes for data movement between memories of different hierarchies in parallel processors is low due to varying memory capacities, access delays, and cache control mechanisms, leading to performance degradation across different OpenCL devices.
Innovation Solution
An arithmetic and control method that acquires and holds attribute groups for read and write blocks, determining a transfer system based on these attributes and configuration parameters to control data movement between memories of different hierarchies, reducing the developer's load and enhancing portability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data movement between memories of different hierarchies is manually controlled by developers, then performance can be optimized for specific devices, but portability of user codes deteriorates across different OpenCL devices
Solution Approach 1:
The system enables self-service by automatically determining data transfer strategies between memory hierarchies. The arithmetic and control unit autonomously analyzes configuration parameters and attribute groups to generate optimal transfer scenarios without requiring developer intervention, thus maintaining performance optimization while ensuring portability across different OpenCL devices.
Solution Approach 2:
The system utilizes parameter changes by varying transfer scenario selection based on configuration parameters and attribute groups. Different transfer scenarios are selected dynamically according to the specific device configuration and data characteristics, enabling both performance optimization for specific devices and portability across different OpenCL implementations.
2Speed
If cache control mechanisms are implemented for each core, then data access speed improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The system applies merging by consolidating cache control functionality into a shared arithmetic and control unit that serves multiple cores. Instead of implementing independent cache control mechanisms for each core, the control unit manages data transfer scenarios for all cores collectively, reducing device complexity and manufacturing cost while maintaining fast data access through optimized transfer scenarios.
3Adaptability or versatility
If multiple transfer scenarios are supported for different data blocks, then performance portability improves, but control logic complexity increases
Solution Approach 1:
The system applies segmentation by dividing the control logic into distinct transfer scenarios, each optimized for specific data block characteristics. The arithmetic and control unit segments the decision-making process into discrete scenario selections based on attribute groups and configuration parameters, making the control logic more manageable and easier to implement while supporting multiple transfer scenarios for different data blocks.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An attribute group storage unit acquires and holds attribute groups set to respective data blocks. A scenario determination unit determines respective transfer systems of the respective blocks between a memory of the lowest hierarchy and a memory of another hierarchy based on those attribute groups and a configuration of an arithmetic unit which is the parallel processor, and controls the transfer of the respective data blocks according to the determined transfer systems, and the parallel arithmetic operation corresponding to the transfer. Each of the attribute groups is necessary to determine the transfer systems, and includes one or more attributes not depending on the configuration of the parallel processor. The attribute groups of the write blocks are set assuming that each of the write blocks has already been located in the memory of another hierarchy, and is transferred to the memory of the lowest hierarchy.