Arithmetic Counter Circuit for Addition-Subtraction Memory Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory technologies lack an efficient counter circuit capable of performing both addition and subtraction counting functions, which are essential for advanced memory operations such as frequency division and timing generation.
Innovation Solution
A counter circuit comprising an addition circuit with multiple stages of counting circuits, a subtraction circuit, and control circuits, which enables addition and subtraction counting by processing carry signals and bit values across stages, and outputs the results in response to specific clock and refresh instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-stage flip-flop structures are used to implement counter circuits, then the counting function can be realized, but the circuit design becomes complex
Solution Approach 1:
The patent replaces the traditional mechanical flip-flop-based counting mechanism with an arithmetic unit-based system. The arithmetic unit performs addition and subtraction operations on storage elements to achieve counting functionality, eliminating the need for complex multi-stage flip-flop structures while maintaining reliable counting operation.
Solution Approach 2:
The arithmetic unit is designed to perform multiple functions including addition, subtraction, and counting operations. By making the arithmetic unit universal, the patent eliminates the need for separate dedicated circuits for different counting operations, thereby reducing overall circuit complexity while maintaining full counting functionality.
2Adaptability or versatility
If traditional counter circuits are used in memory technologies, then basic counting operations are supported, but advanced operations such as frequency division and timing generation cannot be performed
Solution Approach 1:
The arithmetic unit is designed with universal capabilities to perform addition, subtraction, and various derived operations. This multi-functionality enables the circuit to support advanced memory operations including frequency division, timing generation, and other complex counting tasks without requiring separate dedicated circuits for each function.
Solution Approach 2:
The circuit incorporates dynamic control mechanisms that allow the arithmetic unit to adapt its operation mode based on control signals. This dynamic capability enables the same hardware structure to perform different counting operations and support various advanced memory functions by changing operational parameters rather than requiring structural changes.
Data Source
AI summary
A counter circuit includes an addition circuit including counting circuits corresponding to binary bits, a subtraction circuit and control circuits. Each counting circuit obtains a carry signal and this-time bit value according to addend signal and bit value currently output by the counting circuit, outputs the carry signal to next counting circuit, and latches the this-time bit value in response to first clock and outputs same to output terminal of the counting circuit in response to second clock. The subtraction circuit is connected to the counting circuits, obtains present subtraction counting result according to present addition counting result and subtrahend signal and outputs same in response to a first refresh instruction. Each control circuit corresponds to a counting circuit, outputs, in response to second refresh instruction, corresponding bit of the present subtraction counting result to the counting circuit to serve as the bit value output by the counting circuit.