Arithmetic Decoder Segmentation for HDTV Bitstream Processing
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Solution Overview
Problem
Conventional CMOS integrated circuits face challenges in building arithmetic decoders and context memory that operate at the high speeds required for decoding context adaptive binary arithmetic coded video data, particularly for high definition television (HDTV) which demands peak decoding rates of up to 360 Mbits/sec.
Innovation Solution
A system and method for decoding context adaptive binary arithmetic coded data, comprising a symbol interpreter with a first memory, a context adaptive binary arithmetic coded data decoding loop, and a syntax assembler, which generates intermediate binary symbols at a channel rate and decodes them at a consumption rate, utilizing an arithmetic decoder and context memory to manage dynamic context tables efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CMOS integrated circuits are used to build arithmetic decoders and context memory, then device complexity is reduced and manufacturing is easier, but decoding speed cannot reach the required peak rate of 360 Mbits/sec for HDTV
Solution Approach 1:
The patent segments the decoding process into two distinct stages: a high-speed arithmetic decoding stage that operates at the channel rate to generate intermediate binary symbols, and a lower-speed syntax element assembly stage that operates at the consumption rate. This segmentation allows the critical path to be optimized for speed while distributing complexity across multiple modules including parallel arithmetic decoders, context memory banks, and syntax assemblers, thereby achieving 360 Mbits/sec peak decoding rates without overwhelming single-device complexity constraints
Solution Approach 2:
The patent introduces a temporal dimension to the decoding architecture by operating different components at different rates. The arithmetic decoder generates intermediate symbols at the high channel rate, while the syntax assembler consumes them at the lower frame assembly rate. This rate differentiation across time dimensions allows the system to handle peak bandwidth requirements without requiring all components to operate continuously at maximum speed, effectively resolving the speed-complexity contradiction
2Measurement precision
If the context table is updated after each Bin is decoded, then decoding precision is maintained, but parallelization of the decoding process becomes computationally complex
Solution Approach 1:
The patent segments context management into separate functional units: context memory structures that store probability models, arithmetic decoding units that process bins, and context updating logic that maintains precision. Multiple arithmetic decoders can operate in parallel on different data streams while each maintains its own context state, and context updates are performed systematically after each bin decoding without creating complex interdependencies between parallel units, thus preserving precision while enabling parallelization
Solution Approach 2:
The patent uses multiple context memory banks that can be copied or replicated to serve different parallel decoding streams. Each parallel arithmetic decoder unit has access to its own context state, allowing independent operation without complex synchronization. This copying approach maintains decoding precision for each stream while avoiding the complexity of shared resource management in parallel architectures
3Productivity
If intermediate binary symbols are generated at channel rate and then decoded at consumption rate, then high-speed video data can be processed in real-time, but the system requires complex multi-rate interface management
Solution Approach 1:
The patent segments the data flow into two distinct rate domains: a high-speed path for generating intermediate binary symbols from the encoded bitstream at the channel rate, and a lower-speed path for assembling syntax elements at the consumption rate. Buffer memory structures are inserted between these segments to decouple the timing requirements, allowing the high-speed arithmetic decoding to proceed without being constrained by the slower syntax assembly process, thereby achieving real-time processing while managing interface complexity through rate separation
Data Source
AI summary
Presented herein is a system and apparatus for accelerating arithmetic decoding of encoded data. In one embodiment, there is presented a symbol interpreter for decoding CABAC coded data. The symbol interpreter comprises a first memory, a CABAC decoding loop, and a syntax assembler. The first memory receives a bitstream comprising the CABAC coded data at a channel rate. The CABAC decoding loop decodes the CABAC symbols at the channel rate, and comprises an arithmetic decoder for generating binary symbols from the CABAC coded data at the channel rate. The syntax assembler decodes the binary symbols at a consumption rate.