Arithmetic Decoding Circuitry for Video Throughput Bottleneck
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Solution Overview
Problem
Arithmetic decoding in video decoders is a throughput bottleneck due to its data-dependent operations, particularly in high-efficiency entropy-coding tools like arithmetic coding, which complicates the decoding process and slows down the overall decoding speed.
Innovation Solution
The implementation of a high-throughput entropy decoder apparatus with an arithmetic decoding processing circuitry and a variable-length decoder, featuring a context bin decoder, context model update processing circuitry, and error-checking capabilities, along with parallel processing of image units to enhance decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arithmetic decoding is implemented in video decoders to achieve high-efficiency entropy coding, then coding efficiency is improved, but decoding speed deteriorates due to data-dependent operations becoming a throughput bottleneck
Solution Approach 1:
The patent segments the decoding process into two independent parts: arithmetic decoding and variable-length decoding. The arithmetic decoding unit processes the bitstream and outputs intermediate results, which are then processed by the variable-length decoding unit. This segmentation allows each unit to be optimized independently and enables parallel processing, resolving the contradiction between coding efficiency and decoding speed.
Solution Approach 2:
The patent implements preliminary action by performing arithmetic decoding operations in advance and storing the results in a buffer. The variable-length decoding unit can then process these pre-computed results without waiting for the arithmetic decoding to complete, enabling overlapping execution and improving overall throughput.
2Device complexity
If arithmetic decoding and variable-length decoding are performed sequentially in the same decoder unit, then device complexity is reduced, but productivity deteriorates due to the throughput bottleneck
Solution Approach 1:
The patent divides the decoder into separate arithmetic decoding unit and variable-length decoding unit, each with dedicated processing circuits. This segmentation increases device complexity slightly but dramatically improves productivity by enabling parallel processing and eliminating the sequential bottleneck.
Solution Approach 2:
The patent introduces an intermediate buffer between the arithmetic decoding unit and variable-length decoding unit. This buffer acts as an intermediary that decouples the two processing stages, allowing them to operate independently at different rates and improving overall throughput.
3Measurement precision
If arithmetic decoding operations are made data-dependent to achieve high-efficiency entropy coding, then coding precision is improved, but ease of operation deteriorates due to complicated decoding processes
Solution Approach 1:
The patent extracts the complex data-dependent arithmetic decoding operations into a dedicated arithmetic decoding unit with specialized hardware circuits. This extraction maintains the precision benefits while isolating the complexity, allowing the rest of the decoding process to remain simpler and more straightforward.
Data Source
AI summary
An apparatus is capable of achieving high-throughput entropy decoding, and includes an arithmetic decoding processing circuitry and a variable-length decoder (VLD). The arithmetic decoding processing circuitry receives a video bitstream through a bitstream input, applies arithmetic decoding to at least a portion of the video bitstream to derive one or more arithmetic-decoded binary strings containing no arithmetic encoded binary string, and stores the arithmetic-decoded binary strings in the storage device. The variable-length decoder is coupled to the arithmetic decoding processing circuitry, the storage device and a VLD output. The variable-length decoder receives at least a portion of arithmetic-decoded bitstream when arithmetic-decoded bitstreams stored in the storage device are complete for a selected image unit, decodes at least a portion of arithmetic-decoded bitstream into one or more decoded syntax elements, and provides the decoded syntax elements through the VLD output.