Arithmetic Decoding Circuit Using Parallel Comparison Counting
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Solution Overview
Problem
Existing arithmetic decoding methods require numerous branches, leading to inefficiencies and increased time and energy consumption.
Innovation Solution
A dedicated arithmetic decoding circuit integrated into a digital signal processing processor performs parallel comparisons using a table of coefficients and an interval of values, followed by counting identical and successive results to determine the symbol value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If known methods for performing arithmetic decoding are used, then decoding can be performed, but multiple branches at each iteration increase the time required and reduce efficiency
Solution Approach 1:
The patent segments the arithmetic decoding process into distinct functional blocks: a dedicated circuit for performing comparisons and counting results, and a DSP for determining symbol values. This segmentation allows the comparison operations to be executed in parallel without requiring sequential branching, thereby increasing decoding speed and reducing time loss.
Solution Approach 2:
The patent introduces a dedicated comparison circuit as an intermediary component between the input data and the DSP. This intermediary performs the computationally intensive comparison and counting operations, freeing the DSP to focus on symbol determination and reducing the overall decoding time through functional specialization.
2Reliability
If multiple branches are used at each iteration for arithmetic decoding, then symbol decoding can be performed, but the number of processor cycles increases and energy consumption rises
Solution Approach 1:
By segmenting the decoding function into a dedicated comparison circuit and a DSP, the patent eliminates the need for multiple branching operations in the main processing path. The dedicated circuit handles comparisons efficiently in parallel, reducing the number of processor cycles required and thereby lowering energy consumption while maintaining decoding accuracy.
Solution Approach 2:
The patent replaces the traditional sequential branching mechanism with a parallel comparison and counting approach implemented in dedicated hardware. This substitution eliminates the overhead of branch instructions and associated energy consumption, providing a more energy-efficient decoding process that maintains reliability.
3Ease of operation
If numerous connections are made in known arithmetic decoding solutions, then decoding operations can be performed, but device complexity and connection overhead increase
Solution Approach 1:
The patent merges the comparison and counting functions into a single dedicated circuit module. This consolidation reduces the number of separate connections required compared to implementations where these functions are distributed across multiple components, thereby simplifying the overall device architecture while maintaining ease of operation.
Data Source
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AI summary
According to one aspect, a computer system is proposed comprising: - a data memory (MEM) configured to store a table of coefficients (CUM_FREQ2_TAB[]), - a digital signal processing processor (DSP1, DSP2) configured to execute a computer program (PRG1, PRG2) comprising instructions for performing arithmetic decoding from said table of coefficients and an interval of values, - a circuit (HWC1, HWC2) dedicated to said arithmetic decoding, this circuit being configured to: • perform comparisons from the coefficients of said table of coefficients and said interval of values, then • count the results of said comparisons which are identical and successive, the digital signal processing processor (DSP1, DSP2) being configured to determine a value of a symbol associated with said table of coefficients from the number of said identical and successive results counted by said dedicated circuit.