Arithmetic Decoding Circuit Using Parallel Comparison Counts
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Solution Overview
Problem
Existing arithmetic decoding methods require numerous branches at each iteration, leading to inefficiencies and increased time and power consumption.
Innovation Solution
A computer system comprising a digital signal processor and a dedicated circuit that performs comparisons using an array of coefficients and an interval of values, counting identical and successive results, and determining symbol values from these counts, thereby reducing the need for branches and enhancing decoding speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If known arithmetic decoding methods are used with branches at each iteration, then the decoding can be carried out, but the time required increases and efficiency decreases
Solution Approach 1:
The patent extracts the branch operations from the iterative decoding loop and replaces them with a dedicated comparison circuit that performs all necessary comparisons in parallel. This removes the time-consuming branch instructions from the critical decoding path, significantly reducing the time required per iteration while maintaining decoding accuracy.
Solution Approach 2:
The patent replaces the software-based branch logic with a hardware-based comparison circuit. This substitution of mechanical/software operations with dedicated hardware circuitry eliminates the overhead of branch instructions and enables parallel comparison of interval values with coefficient ranges, directly improving decoding speed and efficiency.
2Reliability
If known arithmetic decoding methods with numerous branches are used, then decoding functionality is maintained, but power consumption increases
Solution Approach 1:
The patent extracts power-consuming branch operations from the decoding process and replaces them with a more efficient hardware comparison circuit. This extraction eliminates unnecessary power consumption associated with branch instruction execution while preserving the essential decoding functionality through the dedicated circuit's parallel comparison capability.
Solution Approach 2:
The patent substitutes software-based branch logic with hardware-based comparison circuitry, which consumes less power for the same functional outcome. This replacement reduces dynamic power consumption by eliminating repeated conditional branch operations while maintaining full decoding functionality through the dedicated comparison and counting circuit.
3Ease of operation
If numerous branches are performed at each iteration, then symbol decoding can be achieved, but the number of processor cycles increases
Solution Approach 1:
The patent extracts the iterative branch operations from the processor workflow and consolidates them into a single dedicated comparison circuit that performs all necessary comparisons simultaneously. This extraction reduces the number of processor cycles required while maintaining ease of operation, as the dedicated circuit handles the complexity internally through parallel processing.
Solution Approach 2:
The patent replaces multiple sequential processor-based branch operations with a single hardware comparison circuit that performs parallel comparisons. This substitution dramatically reduces the number of processor cycles needed, as the hardware circuit executes all comparisons in one operation rather than requiring multiple iterative software-based branch instructions.
Data Source
AI summary
A computer system for performing arithmetic decoding includes one or more memories configured to store an array of coefficients and an interval of values. The computer system includes a circuit configured to perform comparisons of the coefficients of the array of coefficients and the interval of values and count the results of the comparisons that are identical and successive. The computer system also includes a digital signal processor configured to determine a value of a symbol associated with the array of coefficients based on the count of identical and successive results.