Arithmetic Decoding with Concatenated ROM-RAM Table Lookup

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Solution Overview

Problem

Current arithmetic coding techniques face limitations in speed and efficiency due to sequential decomposition, narrow registers, and complex product approximations, which hinder significant improvements in throughput and computational complexity, especially for high-frame-rate and UHD video applications.

Innovation Solution

The method employs a concatenated ROM-RAM table lookup and replaces RAM-based tables with a cascade of large ROM and smaller RAM tables, utilizing table lookup for division approximation to enhance arithmetic coding throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If binarization is used to enable arithmetic coding, then compression efficiency is improved, but processing speed deteriorates due to sequential decomposition

Engineering Contradiction:
Improvecompression efficiencyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent pre-calculates and stores arithmetic coding table data in ROM during the design phase. This preliminary action allows the encoder to perform fast table lookups during actual encoding operations, eliminating the need for sequential binary decomposition calculations and significantly improving processing speed while maintaining compression efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the arithmetic coding table in ROM memory, allowing direct lookup of pre-computed values. Instead of performing sequential binary arithmetic operations, the system copies pre-calculated coding values from the ROM table based on input data patterns, dramatically accelerating the encoding process.

Inventive Principle:
Principle #26Copying

2Measurement precision

If narrow registers are used to extract individual data bits, then precision is maintained, but throughput deteriorates due to unavoidable serialization

Engineering Contradiction:
Improvedata precisionVSAvoidthroughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent transitions from sequential bit-by-bit processing in narrow registers to parallel word-level processing using wider registers. By organizing the arithmetic coding table in ROM with multi-bit addresses and retrieving multiple bits simultaneously, the system moves from one-dimensional sequential extraction to multi-dimensional parallel access, maintaining precision while dramatically improving throughput.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If complicated product approximations are defined in serial form, then computational accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvecomputational accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent pre-computes complex product approximation values and stores them in the ROM arithmetic coding table. During operation, the system simply performs table lookups rather than executing complex serial multiplication and approximation algorithms. This preliminary computation transfers the computational burden from the operational phase to the design phase, reducing real-time device complexity while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent copies pre-calculated product approximation values into the ROM table structure. Instead of performing complex serial calculations during encoding, the system retrieves pre-computed approximation values from the table, significantly reducing computational complexity while preserving the accuracy benefits of complicated product approximations.

Inventive Principle:
Principle #26Copying

4Measurement precision

If bisection or binary-tree search is used for decoding, then decoding accuracy is improved, but processing speed deteriorates due to sequential decomposition

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent pre-organizes the arithmetic coding table in ROM with data structured for efficient lookup. Instead of performing sequential bisection or binary-tree search during decoding, the system uses pre-positioned table entries that can be accessed directly through address calculation. This preliminary organization of decoding data eliminates iterative search operations and enables direct access, maintaining decoding accuracy while dramatically improving speed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10455247B2Method and apparatus for performing arithmetic coding on basis of concatenated ROM-RAM table
Publication Date: 2019.10.22 LG ELECTRONICS INC
  • US10455247B2 patent drawing
  • US10455247B2 patent drawing
  • US10455247B2 patent drawing

AI summary

Disclosed herein is a method of performing an arithmetic decoding for data symbols, comprising: creating a decoding table index; obtaining an upper bound value and a lower bound value of a ratio between an interval length and a point within an interval assigned to a symbol from a ROM table; obtaining initial values for a bisection search from a RAM table based on the upper bound value and the lower bound value; and searching a value of sequence in the interval, wherein the interval is determined based on the initial values.