Arithmetic Device Fixed-Point Conversion Sign Extension

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Solution Overview

Problem

Existing techniques for converting signed and unsigned fixed-point numbers into a common format can result in reduced least significant digits, leading to increased calculation errors and limitations in expressing the value of 1, which affects the functionality of neural network circuits.

Innovation Solution

An arithmetic device that includes a conversion unit capable of converting signed and unsigned fixed-point numbers into an extended signed fixed-point number format, ensuring that all original bits are reflected and allowing for accurate representation of values, including 1, by performing sign extension and substituting zeros for insufficient digits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conversion is performed so that the value of 1 can be expressed by adding 2^0 digits, then the value of 1 can be expressed, but the least significant digit of the original fixed-point number is reduced, leading to increased calculation errors

Engineering Contradiction:
Improveability to express value of 1VSAvoidleast significant digit precision
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent extends the bit width of the fixed-point number from 8 bits to 9 bits by adding a new most significant bit position (2^0). This dimensional extension allows the system to represent the value of 1 while preserving all original least significant digits through proper sign extension and zero substitution rules, thereby resolving the contradiction between expressing value 1 and maintaining precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If the value of 1 is not expressed in the converted format, then calculation errors are avoided, but the product-sum operator cannot be used as an adder, deteriorating convenience

Engineering Contradiction:
Improveconvenience of using product-sum operator as adderVSAvoidability to express value of 1
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent changes the bit width parameter from 8 bits to 9 bits and adjusts the decimal point position to accommodate the value of 1. By defining the most significant digit as 2^0 and the least significant digit as 2^-8, the system enables both the representation of value 1 and the use of product-sum operator as adder, eliminating the contradiction between operational convenience and numerical capability.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If sign extension is performed on insufficient digits during conversion, then all original bits are reflected in the extended format, but the conversion complexity increases

Engineering Contradiction:
Improvebit reflection accuracyVSAvoidconversion process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent establishes predetermined conversion rules that are applied automatically during the conversion process. For signed fixed-point numbers, sign extension is performed on insufficient most significant digits, and zeros are substituted for less significant digits. For unsigned fixed-point numbers, zeros are substituted for both insufficient most significant and less significant digits. These preliminary defined rules simplify the conversion process by eliminating the need for complex dynamic decision-making, thereby reducing conversion complexity while maintaining bit reflection accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250181315A1Arithmetic device
Publication Date: 2025.06.05 SONY GROUP CORP
  • US20250181315A1 patent drawing
  • US20250181315A1 patent drawing
  • US20250181315A1 patent drawing

AI summary

Arithmetic devices with error prevention in fixed-point number conversion are disclosed. In, one example, a conversion unit converts a signed fixed-point number in a complement notation of 2 in which a most significant digit and a least significant digit are represented by 2Mi and 2Li, respectively, using integers Mi and Li and an unsigned fixed-point number in which a most significant digit and a least significant digit are represented by 2Mu and 2Lu, respectively, using integers Mu and Lu into an extended signed fixed-point number that is a signed fixed-point number in a complement notation of 2 in which a most significant digit and a least significant digit are represented by 2M and 2L using M and L, respectively, that satisfy the following expression M=max (1, max (Mi, Mu+1)) L=min (0, min (Li, Lu)).