Arithmetic Device Magnetoresistive Elements Write Error Control

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Solution Overview

Problem

Current arithmetic devices face challenges in optimizing computational processing for AI deep learning, particularly in reducing power consumption while maintaining error tolerance, especially in neural networks like convolutional neural networks.

Innovation Solution

The device incorporates a control circuit that sets conditions for write operations in magnetoresistive effect elements based on information related to write errors, using a combination of first and second computational circuits with magnetoresistive effect elements on separate conducting layers, and executes computational processing using signals from these circuits to control voltage and current settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If write operations are performed with high voltage/current to ensure data accuracy, then computational accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvecomputational accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent dynamically adjusts write operation parameters (voltage, current, pulse width) based on the specific computational context, data patterns, and error tolerance requirements. This allows optimization of power consumption while maintaining sufficient computational accuracy for each operation.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system performs write operations with just sufficient strength to achieve the required accuracy level, avoiding excessive voltage/current application. For operations where high precision is not critical, reduced-strength write operations are used to save power.

Inventive Principle:
Principle #16Partial or excessive action

2Use of energy by moving object

If error tolerance is increased to reduce computational requirements, then power consumption is reduced, but computational precision deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidcomputational precision
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The system dynamically adapts error tolerance levels based on the computational task requirements, data importance, and current power constraints. Error tolerance is not fixed but adjusted in real-time to balance power consumption and precision needs.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different error tolerance levels are applied to different computational operations or data elements based on their importance. Critical computations maintain high precision with low error tolerance, while less critical operations can tolerate higher errors for power savings.

Inventive Principle:
Principle #3Local quality

3Productivity

If multiple computational circuits are used to improve processing capability, then computational performance is improved, but device complexity increases

Engineering Contradiction:
Improvecomputational performanceVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple computational circuits are merged into an integrated architecture where they share common resources such as control logic, memory interfaces, and power management units. This reduces overall device complexity while maintaining enhanced computational performance through parallel processing.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption while maintaining computational accuracy by optimizing write operations based on error tolerance, enhancing the overall performance of arithmetic devices in neural network processing.

Implementation Method 1

Arithmetic device having magnetoresistive effect elements

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Data Source

PatentUS11481191B2Arithmetic device having magnetoresistive effect elements
Publication Date: 2022.10.25 KK TOSHIBA
  • US11481191B2 patent drawing
  • US11481191B2 patent drawing
  • US11481191B2 patent drawing

AI summary

According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.