Arithmetic Device Processing Element Group Port Sharing
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Solution Overview
Problem
Existing arithmetic devices for neural networks face challenges in scalable performance improvement due to increased circuit area and lowered operating frequency as the number of processing elements and computation units increases, despite sparse connections between layers.
Innovation Solution
The design includes a first register for input data and multiple processing element groups, each with multiple processing elements, where each group accesses the register through a corresponding port, allowing for efficient multiply-and-accumulate computations and reducing the need for multiple access ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing elements is increased to improve processing performance, then productivity is improved, but device complexity increases due to increased number of ports
Solution Approach 1:
Multiple processing elements share a common port to access the register file. Instead of each processing element having its own dedicated port, multiple ports are merged into a single shared port, allowing multiple processing elements to access the register file through this common interface.
Solution Approach 2:
The shared port serves multiple functions by accommodating access requests from multiple processing elements. The port controller manages this universal interface to handle read and write operations from different processing elements, making the port multi-functional rather than dedicated to a single processing element.
2Productivity
If the number of computation units within processing elements is increased to improve processing performance, then productivity is improved, but device complexity increases due to increased circuit area
Solution Approach 1:
Multiple computation units within processing elements share common resources including the register file access port, control signals, and data pathways. This merging of shared resources reduces the overall circuit area that would otherwise be required if each computation unit had dedicated separate resources.
Solution Approach 2:
The patent introduces a time-multiplexed dimension for resource sharing. Multiple computation units access shared resources at different time slots managed by a controller, effectively adding a temporal dimension to resource allocation. This allows spatial sharing of hardware resources across multiple computation units without requiring physical duplication of each resource.
3Productivity
If the number of ports is increased to allow simultaneous access to more processing elements, then productivity is improved, but operating frequency decreases due to increased circuit area
Solution Approach 1:
Multiple ports are merged into a single shared port with a port controller that manages access from multiple processing elements. This reduction in the number of physical ports decreases circuit area and allows for higher operating frequencies while maintaining the ability to serve multiple processing elements through time-multiplexed access.
Solution Approach 2:
The port controller implements periodic time-slicing to grant access to the shared port to different processing elements in sequence. This periodic action allows multiple processing elements to access the register file systematically without requiring simultaneous dedicated ports for each, thereby reducing circuit area and enabling higher operating frequencies.
Data Source
AI summary
An arithmetic device includes a first register that stores input data as values of a plurality of input neurons, a plurality of ports, and a plurality of processing element groups that correspond to the plurality of ports, respectively, and can access the first register through the respective corresponding ports. Each processing element group includes a plurality of processing elements. Each processing element is associated with at least one of a plurality of output neurons and performs a multiply-and-accumulate computation in which a value of at least one input neuron connected to a corresponding output neuron is multiplied by a weight coefficient and results of multiplication are accumulated.