Arithmetic Memory Unit Cells for Image Sensor Area Reduction
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Solution Overview
Problem
Current image sensors face challenges in reducing design area and power consumption while maintaining performance in various applications such as digital cameras and medical devices.
Innovation Solution
The proposed solution involves a simplified arithmetic memory module with a circuit structure that includes an input block and unit cells to generate a digital difference signal between digital pixel reset and image signals, utilizing multiplexers, inverters, flip/flops, and AND gates to reduce complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional arithmetic memory circuit is used, then image processing functionality is provided, but design area and power consumption increase
Solution Approach 1:
The arithmetic memory is divided into multiple unit cells (first unit cell, second unit cell, third unit cell, etc.), each handling a portion of the arithmetic operation. This segmentation allows parallel processing of different bits of the digital pixel reset signal and digital pixel image signal, reducing overall design area while maintaining processing efficiency.
Solution Approach 2:
Multiple functional components (multiplexers, AND gates, flip-flops) are merged into integrated unit cells. Each unit cell combines signal selection, arithmetic operation, and storage functions, reducing the total number of discrete components and minimizing design area.
2Use of energy by stationary object
If a conventional arithmetic memory circuit is used, then image processing functionality is provided, but power consumption increases
Solution Approach 1:
The arithmetic operations are performed in periodic cycles through clocked flip-flops and multiplexers. Signals are processed in sequential phases (reset signal phase, image signal phase, difference signal phase), reducing simultaneous active components and lowering peak power consumption while maintaining processing throughput.
Solution Approach 2:
Only the essential arithmetic components needed for correlation double sampling are extracted and implemented (multiplexers for signal selection, AND gates for arithmetic operations, flip-flops for storage), eliminating unnecessary circuitry that would increase power consumption.
3Device complexity
If circuit structure is simplified, then design area and power consumption are reduced, but circuit functionality may be compromised
Solution Approach 1:
Each unit cell is designed with specific local functionality tailored to its position in the arithmetic sequence. The first unit cell handles least significant bits, while subsequent unit cells handle more significant bits, with each cell optimized for its specific arithmetic operation requirements, maintaining overall functionality while simplifying individual cell designs.
Solution Approach 2:
The carry output from each unit cell is fed back to the next unit cell's input, creating a ripple-carry arithmetic structure. This feedback mechanism ensures accurate arithmetic operations across all unit cells while using simple, repetitive cell designs that reduce overall circuit complexity.
Data Source
AI summary
Arithmetic memories, image sensors including the arithmetic memories and methods of operating the arithmetic memories are provided. The arithmetic memories may include an input block to which a digital pixel reset signal and a digital pixel image signal are input and a plurality of unit cells configured to generate a digital difference signal. The input block may include first and second multiplexers to which the digital pixel reset signal and the digital pixel image signal are input and an inverter connected to the first multiplexer. The plurality of unit cells may include a first unit cell connected to the input block and a second unit cell through an N-th unit cell successively connected to the first unit cell. N may be two or greater. The first unit cell may include third and fourth multiplexers, a first flip/flop, and a first AND gate.