Arithmetic Module Serial Data Connection Design
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Solution Overview
Problem
Conventional digital signal processors face challenges in reducing power consumption and computation time due to their design, with scalar processors having poor performance and multi-issue processors increasing hardware complexity and power consumption.
Innovation Solution
An arithmetic module with a serial data connection design, employing a Static Floating Point algorithm for normalization and digit alignment, and a digit alignment unit with a multiplexer to optimize data processing and reduce hardware complexity, while using shifters to normalize values between 0.5 and 1, thereby reducing power consumption and computation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If scalar processors are used, then device complexity is reduced, but computation performance deteriorates because they can only process one instruction at a time
Solution Approach 1:
The processor is segmented into multiple specialized execution units (integer execution unit, floating-point execution unit, MAC execution unit) that can operate independently and simultaneously on different instruction types, allowing parallel processing while maintaining manageable complexity through functional specialization
Solution Approach 2:
The patent transitions from single-issue sequential processing to multi-issue parallel processing by adding temporal and functional dimensions to instruction execution, enabling multiple instructions to be processed simultaneously across different execution units rather than sequentially in a single unit
2Productivity
If multi-issue processors are used to improve computation performance, then productivity increases through parallel processing, but device complexity increases due to multiple input and output ports
Solution Approach 1:
The register file is designed as a universal resource that can be accessed by multiple execution units simultaneously, serving as a common data repository that eliminates the need for separate input/output ports for each execution unit, thereby reducing overall port complexity while maintaining parallel processing capability
Solution Approach 2:
Multiple execution units are merged into a unified processor architecture that shares common resources including the register file, instruction memory, and control logic, consolidating what would otherwise require separate input/output interfaces and reducing the N³ growth of ports
3Speed
If multi-issue processors are used, then computation speed increases with parallel processing, but power consumption increases due to increased hardware complexity
Solution Approach 1:
Different execution units are designed with specialized architectures optimized for their specific functions (integer operations, floating-point operations, MAC operations), allowing each unit to operate efficiently at lower power while maintaining high computation speed through functional specialization rather than generic high-power design
Solution Approach 2:
The processor dynamically selects and activates only the execution units needed for the current instruction stream, allowing power consumption to scale with actual computational demand rather than remaining at maximum capacity, thereby achieving high speed when needed while reducing power consumption during less intensive operations
Data Source
AI summary
An arithmetic module is provided, including a first adder, a first shifter coupled to the first adder, a multiplier coupled to the first shifter for receiving an external coefficient signal, a digit alignment unit coupled to the multiplier, a second adder coupled to the digit alignment unit, and a second shifter coupled to the second adder. The arithmetic module reduces the overall computation time effectively, as compared with a scalar processor, by employing a serial data connection design, and also significantly reduces power consumption of the digital signal processor by requiring fewer input and output ends than those of a multi-issue processor.