Arithmetic Processing Device Core Group Cache Coherency
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Solution Overview
Problem
In multi-core processor architectures, the increased size and capacity of last-level caches (LLCs) lead to longer data access paths and higher hit latency, which can slow down memory performance due to frequent access to the main memory for coherency control and write-back operations across multiple LLCs.
Innovation Solution
The implementation of a plurality of core units with shared LLCs, each having a first tag for MESI states and a home agent with a second tag for shared modify states, reduces memory access frequency by managing cache states and data sharing within local core groups, thereby minimizing the need for main memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single large-capacity LLC is shared by all cores, then the cache capacity is increased, but the data access path becomes longer and hit latency increases
Solution Approach 1:
The patent divides the processor into multiple core groups, with each core group having its own dedicated LLC. This segmentation allows each LLC to serve a smaller number of cores, reducing the physical distance and access path length between cores and their dedicated LLC, thereby reducing hit latency while maintaining sufficient cache capacity for each core group.
2Loss of time
If multiple LLCs are provided in a single arithmetic processing device, then the hit latency is reduced, but the frequency of access to main memory increases due to coherency control
Solution Approach 1:
The patent merges the coherency control functions of multiple LLCs into a unified home agent that manages all LLCs. This consolidation allows the home agent to track the state of data across all LLCs and make informed decisions about write-back operations, reducing redundant main memory accesses by determining whether data can be safely discarded or must be written back based on the states stored in both the first tag (MESI state) and second tag (shared modify state).
3Loss of time
If multiple LLCs are provided in a single arithmetic processing device, then the hit latency is reduced, but performance decreases due to frequent main memory access
Solution Approach 1:
The patent implements preliminary action by pre-tracking the state of data in the second tag of the home agent, including whether data is in a shared modify state. This preliminary tracking allows the system to quickly determine during write-back operations whether main memory access is necessary, avoiding unnecessary memory accesses and maintaining high processing performance while benefiting from reduced hit latency.
Data Source
AI summary
An arithmetic processing device includes a plurality of core units, each including a plurality of cores each having a arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent connected to the cache memories provided respectively in the core units; and a memory access controller connected to the home agent and controls access to a main memory. The cache memories each includes a data memory having cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the cache blocks, and the home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared by cache memories, for each of the cache blocks in the cache memories provided respectively in each of the core units.